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參數(shù)資料
| 型號： | DS21552L |
| 英文描述： | 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers |
| 中文描述： | 3.3 DS21352及5V DS21552 T1單芯片收發(fā)器 |
| 文件頁數(shù)： | 102/137頁 |
| 文件大?。?/td> | 1094K |
| 代理商： | DS21552L |
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DS21352/DS21552
102 of 137
Table 19-1 INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE
Instruction
Selected Register
Instruction Codes
SAMPLE/PRELOAD
BYPASS
EXTEST
CLAMP
HIGHZ
IDCODE
Boundary Scan
Bypass
Boundary Scan
Bypass
Bypass
Device Identification
010
111
000
011
100
001
SAMPLE/PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two
functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering
with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows
the device to shift data into the boundary scan register via JTDI using the Shift-DR state.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the
device’s normal operation.
EXTEST
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the
instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel
outputs of all digital output pins will be driven. The boundary scan register will be connected between
JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.
CLAMP
All digital outputs of the device will output data from the boundary scan parallel output while connecting
the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
HIGHZ
All digital outputs of the device will be placed in a high impedance state. The BYPASS register will be
connected between JTDI and JTDO.
EXIT2-IR
A rising edge on JTCLK with JTMS LOW will put the controller in the Update-IR state. The controller
will loop back to Shift-IR if JTMS is HIGH during a rising edge of JTCLK in this state.
UPDATE-IR
The instruction code shifted into the instruction shift register is latched into the parallel output on the
falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the
current instruction. A rising edge on JTCLK with JTMS LOW, will put the controller in the Run-Test-
Idle state. With JTMS HIGH, the controller will enter the Select-DR-Scan state.
相關PDF資料 |
PDF描述 |
|---|---|
| DS21552LN | 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers |
| DS21354 | MTTF is frequently used interchangeably with MTBF |
| DS21354L | 3.3V/5V E1 Single-Chip Transceivers |
| DS21354LN | 3.3V/5V E1 Single-Chip Transceivers |
| DS21354 | 3.3V/5V E1 Single-Chip Transceivers |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS21552L+ | 功能描述:網(wǎng)絡控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21552LB | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS21552LN | 功能描述:網(wǎng)絡控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21552LN+ | 功能描述:網(wǎng)絡控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21554 | 制造商:Maxim Integrated Products 功能描述: |
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