參數(shù)資料
型號(hào): DS2154LNA2+
廠商: Maxim Integrated Products
文件頁數(shù): 95/124頁
文件大?。?/td> 0K
描述: IC TXRX E1 5V 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: E1
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
72 of 124
14.3.
Basic Operation Details
As a basic guideline for interpreting and sending HDLC messages, the following sequences can be
applied:
14.3.1.
Example: Receive an HDLC Message
1. Enable RPS interrupts
2. Wait for interrupt to occur
3. Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt
4. Read RHIR to obtain REMPTY status
a. If REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the FIFO
a1. if CBYTE = 0 then skip to step 5
a2. if CBYTE = 1 then skip to step 7
b. If REMPTY = 1, then skip to step 6
5. Repeat step 4
6. Wait for interrupt, skip to step 4
7. If POK = 0, then discard whole packet, if POK = 1, accept the packet
a. Disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1.
14.3.2.
Example: Transmit an HDLC Message
1. Make sure HDLC controller is done sending any previous messages and is current sending flags by
checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register
2. Enable either the THALF or TNF interrupt
3. Read THIR to obtain TFULL status
a. If TFULL = 0, then write a byte into the FIFO and skip to next step (special case occurs when
the last byte is to be written, in this case set TEOM = 1 before writing the byte and then skip
to step 6)
b. If TFULL = 1, then skip to step 5
4. Repeat step 3
5. Wait for interrupt, skip to step 3
6. Disable THALF or TNF interrupt and enable TMEND interrupt
7. Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
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