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參數(shù)資料
| 型號： | DS21372 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Telecom IC:Other |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數(shù)： | 19/22頁 |
| 文件大?。?/td> | 175K |
| 代理商： | DS21372 |
DS21372
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2. PARALLEL CONTROL INTERFACE
The DS21372 is controlled via a multiplexed bi-directional address/data bus by an external
microcontroller or microprocessor. The DS21372 can operate with either Intel or Motorola bus timing
configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will
be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C.
Electrical Characteristics for more details. The multiplexed bus on the DS21372 saves pins because the
address information and data information share the same signal paths. The addresses are presented to the
pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of
the bus cycle. Addresses must be valid prior to the falling edge of ALE (AS), at which time the DS21372
latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during
the later portion of the DS or WR pulses. In a read cycle, the DS21372 outputs a byte of data during the
latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high
impedance state as RD transitions high in Intel timing or as DS transitions low in Motorola timing. The
DS21372 can also be easily connected to non-multiplexed buses. RCLK and TCLK are used to update
counters and load transmit and receive pattern registers. At slow clock rates, sufficient time must be
allowed for these port operations.
3. PATTERN SET REGISTERS
The Pattern Set Registers (PSR) are loaded each time a new pattern (whether it be pseudorandom or
repetitive) is to be generated. When a pseudorandom pattern is generated, all four PSRs must be loaded
with FF Hex. When a repetitive pattern is to be created, the four PSRs are loaded with the pattern that is
to be repeated. Please see Tables 4 and 5 for some programming examples.
PATTERN SET REGISTERS
(MSB)
(LSB)
PS31
PS30
PS29
PS28
PS27
PS26
PS25
PS24
PSR3 (addr.=00 Hex)
PS23
PS22
PS21
PS20
PS19
PS18
PS17
PS16
PSR2 (addr.=01 Hex)
PS15
PS14
PS13
PS12
PS11
PS10
PS9
PS8
PSR1 (addr.=02 Hex)
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
PSR0 (addr.=03 Hex)
4. PATTERN LENGTH REGISTER
Length Bits LB4 to LB0 determine the length of the pseudorandom polynomial or programmable
repetitive pattern that is generated and detected. With the pseudorandom patterns, the “Tap A” feedback
position of the pattern generator is always equal to the value in the Pattern Length Register (PLR). Please
refer to Figure 2 for a block diagram of the pattern generator and to Tables 4 and 5 for some
programming examples.
相關PDF資料 |
PDF描述 |
|---|---|
| DS2141AN | DATACOM, FRAMER, PDIP40 |
| DS2141AQN | DATACOM, FRAMER, PQCC44 |
| DS2141AQ | DATACOM, FRAMER, PQCC44 |
| DS2141A | DATACOM, FRAMER, PDIP40 |
| DS2143N | DATACOM, FRAMER, PDIP40 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS21372T | 功能描述:網(wǎng)絡控制器與處理器 IC 3.3V Bit Error Rate Tester (BERT) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21372T+ | 功能描述:網(wǎng)絡控制器與處理器 IC 3.3V Bit Error Rate Tester (BERT) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21372TN | 功能描述:網(wǎng)絡控制器與處理器 IC 3.3V Bit Error Rate Tester (BERT) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21372TN+ | 功能描述:網(wǎng)絡控制器與處理器 IC 3.3V Bit Error Rate Tester (BERT) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS214 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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