參數(shù)資料
型號: DS21352L
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, PQFP100
封裝: 14 X 14 MM, LQFP-100
文件頁數(shù): 108/139頁
文件大?。?/td> 1208K
代理商: DS21352L
DS21352/DS21552
70 of 137
15.3.3.2 TRANSMIT AN HDLC MESSAGE
1) Make sure HDLC controller is done sending any previous messages and is current sending flags by checking that the
FIFO is empty by reading the TEMPTY status bit in the TPRM register.
2) Enable either the THALF or TNF interrupt.
3) Read THIR to obtain TFULL status.
a) If TFULL=0, then write a byte into the FIFO and skip to next step (special case occurs when the last byte is to be
written, in this case set TEOM=1 before writing the byte and then skip to step 6).
b) If TFULL=1, then skip to step 5.
4) Repeat step 3.
5) Wait for interrupt, skip to step 3.
6) Disable THALF or TNF interrupt and enable TMEND interrupt.
7) Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
15.3.3.3 TRANSMIT A BOC
1) Write 6–bit code into TBOC.
2) Set SBOC bit in TBOC=1.
15.3.4 HDLC/BOC Register Description
HCR: HDLC CONTROL REGISTER (Address=00 Hex)
(MSB)
(LSB)
RBR
RHR
TFS
THR
TABT
TEOM
TZSD
TCRCD
SYMBOL
NAME AND DESCRIPTION
RBR
HCR.7
Receive BOC Reset. A 0 to 1 transition will reset the BOC circuitry. Must be cleared
and set again for a subsequent reset.
RHR
HCR.6
Receive HDLC Reset. A 0 to 1 transition will reset the HDLC controller. Must be
cleared and set again for a subsequent reset.
TFS
HCR.5
Transmit Flag/Idle Select.
0 = 7Eh
1 = FFh
THR
HCR.4
Transmit HDLC Reset. A 0 to 1 transition will reset both the HDLC controller and the
transmit BOC circuitry. Must be cleared and set again for a subsequent reset.
TABT
HCR.3
Transmit Abort. A 0 to 1 transition will cause the FIFO contents to be dumped and one
FEh abort to be sent followed by 7Eh or FFh flags/idle until a new packet is initiated by
writing new data into the FIFO. Must be cleared and set again for a subsequent abort to
be sent.
TEOM
HCR.2
Transmit End of Message. Should be set to a one just before the last data byte of a
HDLC packet is written into the transmit FIFO at TFFR. This bit will be cleared by the
HDLC controller when the last byte has been transmitted.
TZSD
HCR.1
Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
TCRCD
HCR.0
Transmit CRC Defeat.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
HSR: HDLC STATUS REGISTER (Address=01 Hex)
(MSB)
(LSB)
RBOC
RPE
RPS
RHALF
RNE
THALF
TNF
TMEND
SYMBOL
POSITION
NAME AND DESCRIPTION
RBOC
HSR.7
Receive BOC Detector Change of State. Set whenever the BOC detector sees a
change of state from a BOC Detected to a No Valid Code seen or vice versa. The setting
of this bit prompt the user to read the RBOC register for details.
相關(guān)PDF資料
PDF描述
DS21352LN DATACOM, PCM TRANSCEIVER, PQFP100
DS21552L DATACOM, PCM TRANSCEIVER, PQFP100
DS21552LN DATACOM, PCM TRANSCEIVER, PQFP100
DS21354L DATACOM, PCM TRANSCEIVER, PQFP100
DS21354LN DATACOM, PCM TRANSCEIVER, PQFP100
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