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參數(shù)資料
| 型號(hào)： | DS21349Q+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 17/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/J1 3.3V 28-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 類型： | 線路接口裝置（LIU） |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
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DS21349
24 of 35
Figure 10-1. Loopbacks in the DS21349 Block Diagram
10.2 Internal Pattern Generation and Detection
10.2.1 Transmit Alarm-Indication Signal (TAIS)
When TAIS is enabled (set TAIS in CR2, or pulling the TAIS pin high), the transmitter inputs
TPOS/TNEG and TDATA are ignored and the devices transmits unframed all ones at the transmitter
outputs at the TCLK frequency. If TCLK is not present, then the device uses MCLK to transmit. Both
TAIS and LLB can be enabled at the same time. The transmitter input data is looped back to the receiver
outputs through the jitter attenuator if enabled and the unframed all ones pattern is transmitted at TTIP
and TRING.
10.2.2 Quasirandom Signal Source (QRSS)
The QRSS data pattern is described in AT&T 62411. The pattern is represented by the polynomial 220- 1
with the additional requirement that no more than 14 consecutive 0s be present in the pattern. When
QRSS is enabled (PAT0 = 0 and PAT1 = 1 in CR2 or float the QRSS pin), the data at the transmitter
inputs TPOS/TNEG or TDATA is ignored and replaced by the output of the QRSS pattern generator. In
addition, logic errors can be inserted into the data pattern with a rising edge on the INSLER input pin. If
no logic errors are to be inserted, then the INSLER pin must remain low. If the logic error occurs on the
same clock cycle as a 1 that has been inserted to suppress 15 0s, then the logic error is delayed until the
next clock cycle. The logic error insertion is available in both NRZ and bipolar data modes. Enabling the
QRSS pattern also enables the QRSS detector in the receiver. Pattern synchronization occurs when there
are no errors in 64 bits. When synchronized, the QPD output pin goes low. Once synchronized, an error
in the pattern causes the QPD output to go high for one-half RCLK cycle. In software mode, the level on
the CLKE pin determines the relationship between QPD and RCLK. When CLKE is low, QPD is high
when RCLK is high. When CLKE is high, QPD is high when RCLK is low. The QPD output can be used
to trigger an external bit error counter. When RCL is active or the receiver is not synchronized to the
QRSS pattern, then QPD maintains an output high.
TPOS
TCLK
TNEG
RPOS
RCLK
RNEG
RCL/QPD
NLOOP
TRING
TTIP
RRING
RTIP
MCL
K
Li
ne
D
riv
er
s
CS
U
Filte
rs
Wave
Sh
apin
g
Filte
r
Peak
D
etect
Clo
ck
/Da
ta
Recovery
RCL
De
te
ct
o
r
Transmit
AIS
B8ZS
E
n
co
der
L
o
g
ic
E
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rIn
se
rt
QRSS
B8ZS
D
e
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In-
B
an
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L
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op
C
ode
D
etec
tor
Ji
tter
Att
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ato
r
Local
Loo
pback
QR
SS
D
e
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cto
r
VCO/PLL
In-
B
a
nd
L
oop
G
en.
A
IS
Det
e
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r
LOTC
m
u
x
Rem
o
te
L
o
op
back
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21352 | 制造商:Maxim Integrated Products 功能描述: |
| DS21352DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 T1/J1 Single Chip Tranceiver Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS21352G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Single Chip Transceivers RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21352GN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21352L | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Single Chip Transceivers RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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