參數(shù)資料
型號(hào)： DS21348TN
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Interface
英文描述： DATACOM, PCM TRANSCEIVER, PQFP44
封裝： TQFP-44
文件頁(yè)數(shù)： 33/67頁(yè)
文件大小： 339K
代理商： DS21348TN
DS21348/Q348
39 of 67
8.2.3 Analog Loopback (LLB)
Setting ALB (CCR6.4) to a one puts the DS21348 in Analog Loop Back. Signals at TTIP and TRING
will be internally connected to RTIP and RRING. The incoming signals at RTIP and RRING will be
ignored. The signals at TTIP and TRING will be transmitted as normal. See Figure 3-1 for more details.
8.2.4 Dual Loopback (DLB)
Setting both CCR6.7 and CCR6.6 to a one, LLB and RLB respectively, puts the DS21348 into Dual Loop
Back operation. The TCLK and TPOS/TNEG signals will be looped back through the jitter attenuator (if
enabled) and output at RCLK and RPOS/RNEG. Clock and data recovered from RTIP and RRING will
be looped back to the transmit-side and output at TTIP and TRING. This mode of operation is not
available when implementing hardware operation. See Figure 3-1 for more details.
8.3
PRBS GENERATION & DETECTION
Setting TPRBSE (CCR3.4) = 1 enables the DS21348 to transmit a 2
15-1 (E1) or a 220-1 (T1) Pseudo
Random Bit Sequence (PRBS) depending on the ETS bit setting in CCR1.7. The receive-side of the
DS21348 will always search for these PRBS patterns independent of CCR3.4. The PRBS Bit Error
Output (PBEO) will remain high until the receiver has synchronized to one of the two patterns (64 bits
received without an error) at which time PBEO will go low and the PRBSD bit in the Status Register
(SR) will be set. Once synchronized, any bit errors received will cause a positive going pulse at PBEO,
synchronous with RCLK. This output can be used with external circuitry to keep track of bit error rates
during the PRBS testing. Setting CCR6.0 (ECRS) = 1 will allow the PRBS errors to be accumulated in
the 16-bit counter in registers ECR1 and ECR2. The PRBS synchronizer will remain in sync until it
experiences 6 bit errors or more within a 64 bit span. Both PRBS patterns comply with the ITU-T O.151
specifications.
8.4
ERROR COUNTER
Error Count Register 1 (ECR1) is the most significant word and ECR2 is the least significant word of a
user selectable 16-bit counter that records incoming errors including BiPolar Violations (BPV), Code
Violations (CV), Excessive Zero violations (EXZ) and/or PRBS Errors. See Table 8-3 and Table 8-4 and
Figure 3-2 for details.
Table 8-3 DEFINITION OF RECEIVED ERRORS
ERROR
E1 OR T1
DEFINITION OF RECEIVED ERRORS
BPV
E1/T1
Two consecutive marks with the same polarity. Will ignore BPVs due to
HDB3 and B8ZS zero suppression when CCR2.3 = 0. Typically used with
AMI coding (CCR2.3 = 1). ITU-T O.161.
CV
E1
When HDB3 is enabled (CCR2.3 = 0) and the receiver detects two
consecutive BPVs with the same polarity. ITU-T O.161.
EXZ
E1
When four or more consecutive zeros are detected.
EXZ
T1
When receiving AMI coded signals (CCR2.3 = 1), detection of 16 or more
zeros or a BPV. ANSI T1.403 1999.
When receiving B8ZS coded signals (CCR2.3 = 0), detection of 8 or more
zeros or a BPV. ANSI T1.403 1999.
PRBS
E1/T1
A bit error in a received PRBS pattern. See section 8.3 for details.
ITU-T O.151.
相關(guān)PDF資料
PDF描述
DS21348G DATACOM, PCM TRANSCEIVER, BGA49
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