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參數(shù)資料
| 型號： | DS21348T |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Interface |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PQFP44 |
| 封裝： | TQFP-44 |
| 文件頁數(shù)： | 37/67頁 |
| 文件大小： | 339K |
| 代理商： | DS21348T |
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DS21348/Q348
42 of 67
9.2
TRANSMITTER
The DS21348 uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter
(DAC) to create the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by
the DS21348 meet the latest ETSI, ITU, ANSI, and AT&T specifications. The user will select which
waveform is to be generated by setting the ETS bit (CCR1.7) for E1 or T1 operation, then programming
the L2/L1/L0 bits in Common Control Register 4 for the appropriate application. See Table 9-1 and
Table 9-2 for the proper L2/L1/L0 settings.
A 2.048 MHz or 1.544 MHz TTL clock is required at TCLK for transmitting data at TPOS and TNEG.
ITU specification G.703 requires an accuracy of +/-50 ppm for both T1 and E1. TR62411 and ANSI
specs require an accuracy of +/- 32 ppm for T1 interfaces. The clock can be sourced internally by RCLK
or JACLK. See CCR1.2, CCR1.1, CCR1.0, and Figure 3-3 for details. Due to the nature of the design of
the transmitter in the DS21348, very little jitter (less than 0.005 UIpp broadband from 10 Hz to 100 kHz)
is added to the jitter present on TCLK. Also, the waveforms created are independent of the duty cycle of
TCLK. The transmitter in the DS21348 couples to the E1 or T1 transmit twisted pair (or coaxial cable in
some E1 applications) via a 1:2 step-up transformer.
In order for the device to create the proper
waveforms, the transformer used must meet the specifications listed in Table 9-3.
The DS21348 has automatic short-circuit limiter which limits the source current to 50 mA (rms) into a 1
ohm load. This feature can be disabled by setting the SCLD bit (CCR2.5) = 1. When the current limiter
is activated, TCLE (SR.2) will be set even if short circuit limiter is disabled. The TPD bit (CCR4.0) will
power-down the transmit line driver and tri-state the TTIP and TRING pins. The DS21348 can also
detect when the TTIP or TRING outputs are open circuited. When an open circuit is detected, TOCD
(SR.1) will be set.
9.3
JITTER ATTENUATOR
The DS21348 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via
the JABDS bit (CCR4.2). The 128-bit mode is used in applications where large excursions of wander are
expected. The 32-bit mode is used in delay sensitive applications. The characteristics of the attenuation
are shown in Figure 9-7. The jitter attenuator can be placed in either the receive path or the transmit path
by appropriately setting or clearing the JAS bit (CCR4.3). Also, the jitter attenuator can be disabled (in
effect, removed) by setting the DJA bit (CCR4.1). In order for the jitter attenuator to operate properly, a
2.048 MHz or 1.544 MHz clock must be applied at MCLK. ITU specification G.703 requires an accuracy
of +/-50 ppm for both T1 and E1. TR62411 and ANSI specs require an accuracy of +/- 32 ppm for T1
interfaces. There is an onboard PLL for the jitter attenuator, which will convert the 2.048 MHz clock to a
1.544 MHz rate for T1 applications. Setting JAMUX (CCR1.3) to a logic 0 bypasses this PLL. Onboard
circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the
TCLK pin to create a smooth jitter free clock which is used to clock data out of the jitter attenuator FIFO.
It is acceptable to provide a gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the
transmit side. If the incoming jitter exceeds either 120 UIpp (buffer depth is 128 bits) or 28 UIpp (buffer
depth is 32 bits), then the DS21348 will divide the internal nominal 32.768 MHz (E1) or 24.704 MHz
(T1) clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the
device divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip (JALT) bit in the Receive
Information Register 1 (RIR1).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21348TN | DATACOM, PCM TRANSCEIVER, PQFP44 |
| DS21348G | DATACOM, PCM TRANSCEIVER, BGA49 |
| DS21Q348N | DATACOM, PCM TRANSCEIVER, PBGA144 |
| DS21Q348 | DATACOM, PCM TRANSCEIVER, PBGA144 |
| DS21352L | DATACOM, PCM TRANSCEIVER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21348T+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21348TB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21348TN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21348TN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21348TNB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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