參數(shù)資料
型號(hào)： DS21348GN
廠商： Maxim Integrated Products
文件頁數(shù)： 24/76頁
文件大?。?/td> 0K
描述： IC LIU LN T1/E1/J1 3.3V 49-BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 416
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： T1/E1/J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 49-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 49-CSBGA（7x7）
包裝： 托盤
DS21348/DS21Q348
30 of 76
Table 4-1. MCLK Selection
MCLK
(MHz)
JAMUX
(CCR1.3)
ETS
(CCR1.7)
2.048
0
2.048
1
1.544
0
1
CCR2 (01H): COMMON CONTROL REGISTER 2
(MSB)
(LSB)
P25S
n/a
SCLD
CLDS
RHBE
THBE
TCES
RCES
SYMBOL
POSITION
DESCRIPTION
P25S
CCR2.7
Pin 25 Select. Forced to logic 0 in hardware mode.
0 = toggles high during a Receive Carrier Loss condition
1 = toggles high if TCLK does not transition for at least 5
s
-
CCR2.6
Not Assigned. Should be set to zero when written to.
SCLD
CCR2.5
Short Circuit Limit Disable (ETS = 0). Controls the 50 mA (rms)
current limiter.
0 = enable 50 mA current limiter
1 = DISABLE 50 MA CURRENT LIMITER
CLDS
CCR2.4
Custom Line Driver Select. Setting this bit to a one will redefine the
operation of the transmit line driver. When this bit is set to a one and
CCR4.5 = CCR4.6 = CCR4.7 = 0, then the device will generate a square
wave at the TTIP and TRING outputs instead of a normal waveform.
When this bit is set to a one and CCR4.5 = CCR4.6 = CCR4.7
≠ 0, then
the device will force TTIP and TRING outputs to become open drain
drivers instead of their normal push-pull operation. This bit should be set
to zero for normal operation of the device. Contact the factory for more
details on how to use this bit.
RHBE
CCR2.3
Receive HDB3/B8ZS Enable. See Figure 1-2.
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
THBE
CCR2.2
Transmit HDB3/B8ZS Enable. See Figure 1-3.
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
TCES
CCR2.1
Transmit Clock Edge Select. Selects which TCLK edge to sample TPOS
and TNEG. See Figure 1-3.
0 = sample TPOS and TNEG on falling edge of TCLK
1 = sample TPOS and TNEG on rising edge of TCLK
RCES
CCR2.0
Receive Clock Edge Select. Selects which RCLK edge to update RPOS
and RNEG. See Figure 1-2.
0 = update RPOS and RNEG on rising edge of RCLK
1 = update RPOS and RNEG on falling edge of RCLK
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21348GN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348GNB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348GN-C01 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348T 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348T+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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