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參數(shù)資料
| 型號(hào)： | DS21348GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 8/76頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 3.3V 49-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 416 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 49-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 49-CSBGA（7x7） |
| 包裝： | 托盤 |
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DS21348/DS21Q348
16 of 76
NAME
PIN
I/O
FUNCTION
TTIP/
TRING
34/37
O
Transmit Tip and Ring [TTIP AND TRING]. Analog line driver
outputs. These pins connect via a step-up transformer to the line. See
Section 5 for details.
VDD
21/36
—
Positive Supply. 3.3V ±5%
VSM
20
I
Voltage Supply Mode. Should be low for 3.3V operation.
VSS
22/35
—
Signal Ground
WR (R/W)
3
I
Write Input (Read/Write), Active Low. See the bus timing
diagrams in Section 11.
Table 2-6. Pin Descriptions in Serial Port Mode (Sorted By Pin Name,
DS21348T Pin Numbering)
NAME
PIN
I/O
FUNCTION
BIS0/BIS1
32/33
I
Bus Interface Select Bits 0 and 1. Used to select bus interface
option. See Table 2-1 for details.
BPCLK
31
O
Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz
output.
CS
1
I
Chip Select, Active Low. Active-low signal must be low to read or
write to the device.
HRST
29
I
Hardware Reset, Active Low. Bringing
HRST low will reset the
DS21348 setting all control bits to their default state of all zeros.
ICES
8
I
Input Clock Edge Select. Selects whether the serial port data input
(SDI) is sampled on rising (ICES =0) or falling edge (ICES = 1) of
SCLK.
INT
23
O
Interrupt, Active Low. Flags host controller during conditions and
change of conditions defined in the Status Register. Active-low,
open-drain output.
MCLK
30
I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional.
NA
—
I
Not Assigned. Should be tied low.
OCES
9
I
Output Clock Edge Select. Selects whether the serial port data
output (SDO) is valid on the rising (OCES = 1) or falling edge
(OCES = 0) of SCLK.
PBEO
24
O
PRBS Bit Error Output. The receiver will constantly search for a
215-1 or a 220-1 PRBS depending on the ETS bit setting (CCR1.7).
Remains high if out of synchronization with the PRBS pattern. Goes
low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2
registers by setting CCR6.2 to a logic 1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21348GN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21348GNB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21348GN-C01 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21348T | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21348T+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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