參數(shù)資料
型號(hào): DS21348G
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, BGA49
封裝: CABGA-49
文件頁(yè)數(shù): 19/67頁(yè)
文件大?。?/td> 339K
代理商: DS21348G
DS21348/Q348
26 of 67
6.1
DEVICE POWER-UP & RESET
The DS21348 will reset itself upon power-up setting all writeable registers to 00h and clear the status and
information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After the
power supplies have settled following power-up, initialize all control registers to the desired settings, then
toggle the LIRST bit (CCR3.2). At anytime, the DS21348 can be reset to the default settings by bringing
HRST* (pin 29) low (level triggered) or by powering down and powering up again.
CCR4 (03H): COMMON CONTROL REGISTER 4
(MSB)
(LSB)
L2
L1
L0
EGL
JAS
JABDS
DJA
TPD
SYMBOL
POSITION
NAME AND DESCRIPTION
L2
CCR4.7
Line Build Out Select Bit 2. Sets the transmitter build out; see
Table 9-1 for E1 and Table 9-2 for T1.
L1
CCR4.6
Line Build Out Select Bit 1. Sets the transmitter build out; see
Table 9-1 for E1 and Table 9-2 for T1.
L0
CCR4.5
Line Build Out Select Bit 0. Sets the transmitter build out; see
Table 9-1 for E1 and Table 9-2 for T1.
EGL
CCR4.4
Receive Equalizer Gain Limit. This bit controls the
sensitivity of the receive equalizer. See Table 6-2.
JAS
CCR4.3
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
JABDS
CCR4.2
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
DJA
CCR4.1
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
TPD
CCR4.0
Transmit Power Down.
0 = normal transmitter operation
1 = powers down the transmitter and tri-states the TTIP and
TRING pins
Table 6-2 RECEIVE SENSITIVITY SETTINGS
EGL
(CCR4.4)
ETS
(CCR1.7)
RECEIVE SENSITIVITY
0
0 (E1)
-12 dB (short haul)
1
0 (E1)
-43 dB (long haul)
1
1 (T1)
-30 dB (limited long haul)
0
1 (T1)
-36 dB (long haul)
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