參數(shù)資料
型號： DS21348G
英文描述： 3.3V E1/T1/J1 Line Interface
中文描述： 3.3 E1/T1/J1線路接口
文件頁數(shù)： 12/73頁
文件大?。?/td> 551K
代理商： DS21348G
DS21348/Q348
12 of 73
ACRONYM
PIN
I/O
DESCRIPTION
RCLK
40
O
Receive Clock.
Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
Read Input (Data Strobe).
RD* and DS* are active low signals.
DS active low when in nonmultiplexed, Motorola mode. See the
Bus
Timing Diagrams
in Section 12.
Receive Carrier Loss/Loss of Transmit Clock.
An output which
will toggle high during a receive carrier loss (CCR2.7 = 0) or will
toggle high if the TCLK pin has not been toggled for 5 sec 2
sec (CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware
mode.
Receive Negative Data.
Updated on the rising edge (CCR2.0 = 0)
or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out
of the line interface. Set NRZE (CCR1.6) to a one for NRZ
applications. In NRZ mode, data will be output on RPOS while a
received error will cause a positive-going pulse synchronous with
RCLK at RNEG. See Section 8.4 for details.
Receive Positive Data.
Updated on the rising edge (CCR2.0 = 0) or
the falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the
line interface. Set NRZE (CCR1.6) to a one for NRZ applications. In
NRZ mode, data will be output on RPOS while a received error will
cause a positive-going pulse synchronous with RCLK at RNEG. See
Section 8.4 for details.
Receive Tip and Ring.
Analog inputs for clock recovery circuitry.
These pins connect via a 1:1 transformer to the line. See Section 7
for details.
Transmit Clock.
A 2.048MHz or 1.544MHz primary clock. Used to
clock data through the transmit side formatter. Can be sourced
internally by MCLK or RCLK. See Common Control Register 1 and
Figure 3-3.
3-State Control.
Set high to 3-state all outputs and I/O pins
(including the parallel control port). Set low for normal operation.
Useful in board level testing.
Transmit Negative Data.
Sampled on the falling edge (CCR2.1 =
0) or the rising edge (CCR2.1 = 1) of TCLK for data to be
transmitted out onto the line.
Transmit Positive Data.
Sampled on the falling edge (CCR2.1 = 0)
or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted
out onto the line.
Transmit Tip and Ring [TTIP & TRING].
Analog line driver
outputs. These pins connect via a step-up transformer to the line. See
Section 7 for details.
Positive Supply.
5.0V ±5%
RD*
(DS*)
2
I
RCL/
LOTC
25
O
RNEG
39
O
RPOS
38
O
RTIP/
RRING
27/
28
I
TCLK
43
I
TEST
26
I
TNEG
42
I
TPOS
41
I
TTIP/
TRING
34/
37
O
V
DD
21/
36
20
22/
35
-
VSM
V
SS
I
-
Voltage Supply Mode.
Should be tied high for 5V operation.
Signal Ground.
相關(guān)PDF資料
PDF描述
DS21348GN 3.3V E1/T1/J1 Line Interface
DS21348 3.3V E1/T1/J1 Line Interface
DS21348T 3.3V E1/T1/J1 Line Interface
DS21348TN 3.3V E1/T1/J1 Line Interface
DS21352 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21348G+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348G+W 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348GB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348GN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348GN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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