參數(shù)資料
型號: DS2016-150
英文描述: IRON HOLDER;
中文描述: 2k × 8 3V/5V運行靜態(tài)RAM
文件頁數(shù): 7/9頁
文件大?。?/td> 254K
代理商: DS2016-150
DS2016
7 of 9
TIMING DIAGRAM: DATA RETENTION - POWER-UP, POWER-DOWN
Figure 1
SEE NOTE 8
NOTES:
1.
WE
is high for read cycles.
2.
OE
= V
IH
or V
IL
. If
OE
= V
IH
during write cycle, the output buffers remain in a high impedance
state.
3.
t
WP
is specified as the logical AND of
CE
and
WE
. t
WP
is measured from the latter of
CE
or
WE
going low to the earlier of
CE
or
WE
going high.
4.
t
DH
and t
DS
are measured from the earlier of
CE
or
WE
going high.
5.
If the
CE
low transition occurs simultaneously with or later than the
WE
low transition, the
output buffers remain in a high impedance state.
6.
If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
buffers remain in a high impedance state.
7.
If
WE
is low or the
WE
low transition occurs prior to or simultaneously with the
CE
low
transition, the output buffers remain in a high impedance state.
8.
If the V
IH
level of CE is 2.0V during the period that V
CC
voltage is going down from 4.5V to
2.7V, I
CCS1
current flows.
9.
The DS2016 maintains full operation from 5.5V to 2.7V. The electrical characteristics tables show
two tested and guaranteed points of operation. For operation between 4.5V and 3.5 volts, use the
composite worst case characteristics from both 5V and 3V operation for design purposes.
DC TEST CONDITIONS
Outputs Open
All voltages are referenced to ground.
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0V - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5 ns
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