參數(shù)資料
型號: DS1859B-050/T&R
廠商: Maxim Integrated Products
文件頁數(shù): 5/28頁
文件大?。?/td> 0K
描述: IC RES TEMP 50/50K W/3MON 16-BGA
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
接片: 256
電阻(歐姆): 50k
電路數(shù): 2
溫度系數(shù): 標準值 50 ppm/°C
存儲器類型: 非易失
接口: I²C(設備位址)
電源電壓: 2.85 V ~ 5.5 V
工作溫度: -40°C ~ 95°C
安裝類型: 表面貼裝
封裝/外殼: 16-LBGA,CSPBGA
供應商設備封裝: 16-CSBGA(4x4)
包裝: 帶卷 (TR)
DS1859
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
____________________________________________________________________
13
MEMORY LOCATION
(hex)
EEPROM/SRAM
R/W
DEFAULT SETTING
(hex)
NAME OF LOCATION
FUNCTION
00 to 7F
EEPROM
R/W
00
Standards Data
Auxiliary Device
MEMORY
LOCATION
(hex)
EEPROM/
SRAM
R/W
DEFAULT
SETTING
(hex)
NAME OF LOCATION
FUNCTION
00 to 01
EEPROM
R/W
00
TMPlimhi (MSB to LSB)
Contains upper limit settings for temperature.
If the limit is violated, an alarm flag in Main
Device byte 70h is set.
02 to 03
EEPROM
R/W
00
TMPlimlo (MSB to LSB)
Contains lower limit settings for temperature. If
the limit is violated, an alarm flag in Main
Device byte 70h is set.
04 to 05
EEPROM
R/W
00
TMPwrnhi (MSB to LSB)
Contains upper limit settings for temperature.
If the limit is violated, a warning flag in Main
Device byte 74h is set.
06 to 07
EEPROM
R/W
00
TMPwrnlo (MSB to LSB)
Contains lower limit settings for temperature. If
the limit is violated, a warning flag in Main
Device byte 74h is set.
08 to 09
EEPROM
R/W
00
VCClimhi (MSB to LSB)
Contains upper limit settings for VCC. If the
limit is violated, an alarm flag in Main Device
byte 70h is set.
0A to 0B
EEPROM
R/W
00
VCClimlo (MSB to LSB)
Contains lower limit settings for VCC. If the
limit is violated, an alarm flag in Main Device
byte 70h is set.
0C to 0D
EEPROM
R/W
00
VCCwrnhi (MSB to LSB)
Contains upper limit settings for VCC. If the
limit is violated, a warning flag in Main Device
byte 74h is set.
0E to 0F
EEPROM
R/W
00
VCCwrnlo (MSB to LSB)
Contains lower limit settings for VCC. If the
limit is violated, a warning flag in Main Device
byte 74h is set.
10 to 11
EEPROM
R/W
00
MON1limhi (MSB to LSB)
Contains upper limit settings for MON1. If the
limit is violated, an alarm flag in Main Device
byte 70h is set.
Main Device
Note: SRAM defaults are power-on defaults. EEPROM defaults are factory defaults.
Register Map
A description of the registers is below. The registers
are read only (R) or read/write (R/W). The R/W registers
are writable only if write protect has not been asserted
(see the Memory Description section).
Bytes designated as "Reserved" have been set aside
for added functionality in future revisions of this device.
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