Memory access to the DS1852 is through the 2-wire interface. See the 2-WIRE OPERATION section. The memory within the" />
參數資料
型號: DS1852B-00C+T&R
廠商: Maxim Integrated Products
文件頁數: 6/26頁
文件大?。?/td> 0K
描述: IC MONITOR TXRX OPTICAL 25-BGA
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
類型: 收發(fā)器
電源電壓: 2.7 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 25-TFBGA,CSPBGA
供應商設備封裝: 25-BGA(5x5)
包裝: 帶卷 (TR)
DS1852
14 of 26
MEMORY MAP
Memory access to the DS1852 is through the 2-wire interface. See the 2-WIRE OPERATION section.
The memory within the DS1852 is organized into multiple tables. The lower 128 bytes of memory are
common to all tables, the upper 128 bytes are addressed according to the table select byte at 7Fh. Valid
values of the table address byte are 00h to 03h, to access Tables 00h through 03h.
*For permission details of this memory block refer to following table.
The following tables detail the memory contents. Where descriptions are underlined an expanded table
indicates the function of individual bits within the byte. The reserved memory locations should not be
used even though R/W access may be possible.
Not all memory is EEPROM; RAM cells are shaded within the tables, and denoted beneath.
Tables 00h –
03h
Lower
128 bytes
R- All
W - Level 2*
80h
Table 00h
Upper
128 Bytes
No Physical
Memory
Table 03h
Upper
128 Bytes
R/W - Level 2
Table 02h
Upper
128 Bytes
R/W - Level 2
Table 01h
Upper
128 Bytes
R/W - Level 1
FF
80h
FF
00h
7Fh
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