參數(shù)資料
型號： DS1848B-050+T&R
廠商： Maxim Integrated Products
文件頁數(shù)： 13/17頁
文件大?。?/td> 0K
描述： IC RES/MEM TEMP 50/10K 16-BGA
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,500
接片： 256
電阻（歐姆）： 10k，50k
電路數(shù)： 2
溫度系數(shù)： 標準值 850 ppm/°C
存儲器類型： 非易失
接口： I²C（設備位址）
電源電壓： 3 V ~ 5.5 V
工作溫度： -40°C ~ 95°C
安裝類型： 表面貼裝
封裝/外殼： 16-LBGA，CSPBGA
供應商設備封裝： 16-CSBGA（4x4）
包裝： 帶卷 (TR)
DS1848
5 of 17
Memory Location Name of Location
Function of Location
With AEN = 0 the user can operate in a test
mode. Address updates made from the
temperature sensor will cease. The user can load a
memory location into E4h and verify that the
values in locations F0h and F1h are the expected
user-defined values.
E2h
Temperature MSB
This byte contains the MSB of the 13-bit 2s
complement temperature output from the
temperature sensor.
E3h
Temperature LSB
This byte contains the LSB of the 13-bit 2s
complement temperature output from the
temperature sensor.
For example temperature readings, refer to Table
2.
E4h
Address Pointer
Calculated, current resistor address (0h – 47h).
The user-defined resistor setting at this location in
the respective look-up table will be loaded into
F0h and F1h to set the two resistors.
E5h to E6h
User Memory
General purpose user memory (SRAM)
E7h
Address Select
Internal or external device address select. This
byte allows the user to use the external address
pins or an internal register location to determine
the device address.
ENB = 0 and external A2, A1, A0 grounded,
device will use internal address bits (A2, A1, A0)
in this register
ENB = 1, external A2, A1, A0 = any setting,
device will use external address pins
Default setting is 01h. The device uses external
pins to determine its address.
E8h to EFh
User Memory
General purpose user memory (SRAM)
F0h
Resistor 0 Setting
In the user-controlled setting mode, this block
contains the resistor 0 setting.
F1h
Resistor 1 Setting
In the user-controlled setting mode, this block
contains the resistor 1 setting.
F2h to FFh
User memory
General purpose user memory (SRAM)
S 27 26 25 24 23 22 21
20 2-1 2-2 2-3 2-4 X X X
A2 A1 A0 ENB
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