參數(shù)資料
型號: DS17887-3
廠商: DALLAS SEMICONDUCTOR
元件分類: Timer or RTC
英文描述: 1 TIMER(S), REAL TIME CLOCK, DMA24
封裝: PLASTIC, MODULE, DIP-24
文件頁數(shù): 11/18頁
文件大?。?/td> 343K
代理商: DS17887-3
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +5.5V, VDD = +3.0V to +5.5V, TA = 0°C to +70°C. Typical values are at TA = +25°C, VCC = +5.0V, VDD = +3.3V,
unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range (relative to VSS) at VDD, VCC,
CLOCK_D, DATA_D, CLOCK_C, DATA_C,
DRVR_EN, MODE ..................................................-0.5V to +6.0V
Continuous Power Dissipation (TA = +70°C)
(derate 11.1mW/°C above +70°C) ..............................889mW
Voltage Range (relative to VSS) at GND_REF .......-0.5V to +0.5V
Operating Junction Temperature (TJ) Range ....-55°C to +150°C
Storage Ambient Temperature (TS) Range .......-40°C to +150°C
Electrostatic Discharge (ESD)
Human Body Model......................................................> ±3kV
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
Supply Voltage
VCC or VDD
See the Applications Information section
(Note 1)
3.0
5.5
V
ICC
VCC = 5.5V, VDD = 5.5V, 100kbps,
60pF load on cable, 10pF load on display,
current into VCC pin
1.3
3.0
Supply Current
IDD
VCC = 5.5V, VDD = 5.5V, 100kbps,
60pF load on cable, 10pF load on display,
current into VDD pin
4.3
7.0
mA
DC to 500kHz
100
Supply Noise Tolerance
DC to 60Hz (series mode)
700
mVP-P
CLOCK_C, DATA_C, CLOCK_D, DATA_D (Notes 2, 3)
Cable side (CLOCK_C, DATA_C)
VCC - 0.1
VCC
Output-High Voltage
VOH
Display side (CLOCK_D, DATA_D)
VDD - 0.1
VDD
V
VOL
VOL achieved within 1μs of negative
transition (see Figure 1a, State 2)
0.2
0.4
V
Cable
side
15
Output-Low Voltage
VHOLD
After VOL is achieved, VHOLD is
the most positive level allowed
if logic level is 0 and no other
driver is asserting low on the
same node (series mode)
Display
side
20
% of
Supply
High-to-Low Threshold
VTRIGIH
Threshold used to detect high-to-low
transition relative to supply (VCC for cable
side, VDD for display side)
75
% of
Supply
Cable
side
12.5
Low-to-High Threshold
VTRIGIL
Threshold used to detect low-to-
high transition relative to supply
(VCC for cable side, VDD for
display side)
Display
side
17.5
% of
Supply
Output-High-State Current Limit
Output in ramp-up mode for DATA_C
5.0
16.5
mA
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