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參數(shù)資料
| 型號(hào)： | DS1746-70IND |
| 英文描述： | Y2K-Compliant, Nonvolatile Timekeeping RAMs |
| 中文描述： | 千年蟲(chóng)的，非易失時(shí)鐘存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 5/18頁(yè) |
| 文件大小： | 224K |
| 代理商： | DS1746-70IND |
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DS1746/DS1746P
5 of 18
DS1746 REGISTER MAP
Table 2
DATA
ADDRESS
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
10 YEAR
X X X
10 MO
X X
10 DATE
BF FT X X X
X X
10 HOUR
X
10 MINUTES
OSC
10 SECONDS
W R
10 CENTURY
OSC = STOP BIT
R = READ BIT
W = WRITE BIT
X = SEE NOTE BELOW
FUNCTION/RANGE
1FFFF
1FFFE
1FFFD
1FFFC
1FFFB
1FFFA
1FFF9
1FFF8
YEAR
MONTH
DATE
DAY
HOUR
MINUTES
SECONDS
CENTURY
YEAR
MONTH
DATE
DAY
HOUR
MINUTES
SECONDS
CENTURY
00-99
01-12
01-31
01-07
00-23
00-59
00-59
00-39
FT = FREQUENCY TEST
BF = BATTERY FLAG
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1746 is in the read mode wheneverOE (output enable) is low,WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within t
AA
after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times
and states are not met, valid data will be available at the latter of chip enable access (t
CEA)
or at output
enable access time (t
OEA)
. The state of the data input/output pins (DQ) is controlled by CE and OE. If the
outputs are activated before t
AA
, the data lines are driven to an intermediate state until t
AA
. If the address
inputs are changed while CE and OE remain valid, output data will remain valid for output data hold
time (t
OH
) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1746 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE, or CE. The addresses must be held valid throughout
the cycle. CE or WEmust return inactive for a minimum of t
WR
prior to the initiation of another read or
write cycle. Data in must be valid t
DS
prior to the end of write and remain valid for t
DS
afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus contention. If OE is low prior to
WEtransitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WEwill then disable the output t
WEZ
after WEgoes active.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1746P-70IND | Y2K-Compliant, Nonvolatile Timekeeping RAMs |
| DS1746W-120IND | Y2K-Compliant, Nonvolatile Timekeeping RAMs |
| DS1746WP-120 | Y2K-Compliant, Nonvolatile Timekeeping RAMs |
| DS1746WP-120IND | Y2K-Compliant, Nonvolatile Timekeeping RAMs |
| DS1746 | Y2K-Compliant, Nonvolatile Timekeeping RAMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1746-70IND+ | 功能描述:實(shí)時(shí)時(shí)鐘 Timekeeping NV RAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1746P | 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:Y2K-Compliant, Nonvolatile Timekeeping RAMs |
| DS1746P/YP/WP | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:PowerCap with Crystal |
| DS1746P-70 | 功能描述:實(shí)時(shí)時(shí)鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1746P-70+ | 功能描述:實(shí)時(shí)時(shí)鐘 Timekeeping NV RAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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