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參數(shù)資料
| 型號： | DS1744P |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Timer or RTC |
| 英文描述： | REAL TIME CLOCK, DMA34 |
| 封裝： | POWERCAP MODULE-34 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 225K |
| 代理商： | DS1744P |
DS1744/DS1744P
5 of 18
DS1744 REGISTER MAP Table 2
DATA
ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
FUNCTION/RANGE
7FFF
10 YEAR
YEAR
00-99
7FFE
X
10 MO
MONTH
01-12
7FFD
X
10 DATE
DATE
01-31
7FFC
BF
FT
X
DAY
01-07
7FFB
X
10 HOUR
HOUR
00-23
7FFA
X
10 MINUTES
MINUTES
00-59
7FF9
OSC
10 SECONDS
SECONDS
00-59
7FF8
W
R
10 CENTURY
CENTURY
00-39
OSC = STOP BIT
R
= READ BIT
FT = FREQUENCY TEST
W
= WRITE BIT
X
= SEE NOTE BELOW
BF = BATTERY FLAG
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1744 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and
CE (chip enable) is low. The device architecture allows ripple-through access to any of the address
locations in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address
input is stable, providing that the CE and OE access times and states are satisfied. If CE or OE access
times and states are not met, valid data will be available at the latter of chip enable access (tCEA) or at
output enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE .
If the outputs are activated before tAA , the data lines are driven to an intermediate state until tAA . If the
address inputs are changed while CE and OE remain valid, output data will remain valid for output data
hold time (tOH) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1744 is in the write mode whenever WE , and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid t DS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the output tWEZ after WE goes active.
相關PDF資料 |
PDF描述 |
|---|---|
| DS1744 | REAL TIME CLOCK, DMA28 |
| DS1746-70 | 0 TIMER(S), REAL TIME CLOCK, DIP32 |
| DS1746WP-120 | 0 TIMER(S), REAL TIME CLOCK, DMA34 |
| DS1746W-120 | 0 TIMER(S), REAL TIME CLOCK, DIP32 |
| DS1746P-70 | 0 TIMER(S), REAL TIME CLOCK, DMA34 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS1744P/YP/WP | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:PowerCap with Crystal |
| DS1744P-70 | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1744P-70+ | 功能描述:實時時鐘 Timekeeping NV RAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1744P-70IND | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1744P-70IND+ | 功能描述:實時時鐘 Timekeeping NV RAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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