參數(shù)資料
型號(hào): DS1721U+T&R
廠商: Maxim Integrated
文件頁(yè)數(shù): 8/17頁(yè)
文件大?。?/td> 257K
描述: IC THERMOMETER/STAT DIG HP 8USOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 3,000
功能: 溫度計(jì),恒溫計(jì)
傳感器類(lèi)型: 內(nèi)部
感應(yīng)溫度: -55°C ~ 125°C
精確度: ±2°C(最小值)
拓?fù)洌?/td> ADC,比較器,寄存器庫(kù)
輸出類(lèi)型: 2 線串行,I²C?/SMBUS?
輸出警報(bào):
輸出風(fēng)扇:
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -55°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 帶卷 (TR)
DS1721
 
 
 
8 of 17
DATA TRANSFER ON 2-WIRE SERIAL BUS Figure 5
 
 
 
Figure 6 details how data transfer is accomplished on the two-wire bus. Depending upon the state of the
R/
W  bit, two types of data transfer are possible: 
 
Data transfer from a master transmitter to a slave receiver. The 1
st
 byte transmitted by the master is
the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each
received byte.
 
Data transfer from a slave transmitter to a master receiver. The  1
st
  byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned.
 
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released.
 
The DS1721 may operate in the following two modes:
 
Slave receiver mode: Serial  data  and  clock  are  received  through  SDA  and  SCL.  After  each  byte  is 
received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is performed by hardware after reception of
the slave address and direction bit.
 
Slave transmitter mode: The first byte is received and handled as in the slave receiver mode. However, 
in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted
on SDA by the DS1721 while the serial clock is input on SCL. START and STOP conditions are
recognized as the beginning and end of a serial transfer.
 
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