參數(shù)資料
型號: DS1706P
英文描述: 3.3 and 5.0 Volt MicroMonitor
中文描述: 3.3和5.0伏特MicroMonitor
文件頁數(shù): 2/10頁
文件大小: 76K
代理商: DS1706P
DS1705/DS1706
011296 2/10
The second function the DS1705/DS1706 performs is
pushbutton reset control. The DS1705/DS1706
debounces the pushbutton input and guarantees an
active reset pulse width of 130 ms minimum.
The third function is a watchdog timer. The
DS1705/DS1706 has an internal timer that forces the
WDO signal to the active state if the strobe input is not
driven low prior to time–out.
OPERATION
Power Monitor
The DS1705/DS1706 detects out–of–tolerance power
supply conditions and warns a processor–based sys-
tem of impending power failure. When V
CC
falls below
the minimum V
CC
tolerance, a comparator outputs the
RST (or RST) signal. RST (or RST) is an excellent con-
trol signal for a microprocessor, as processing is
stopped at the last possible moment of valid V
CC
. On
power–up, RST (or RST) are kept active for a minimum
of 130 ms to allow the power supply and processor to
stabilize.
Pushbutton Reset
The DS1705/DS1706 provides an input pin for direct
connection to a push–button reset (see Figure 2). The
pushbutton reset input requires an active low signal.
Internally, this input is debounced and timed such that a
RST (or RST) signal of at least 130 ms minimum will be
generated. The 130 ms delay commences as the push-
button reset input is released from the low level. The
push–button can be initiated by connecting the WDS or
NMI outputs to the PBRST input as shown in Figure 3.
Non–Maskable Interrupt
The DS1705/DS1706 generates a non–maskable inter-
rupt (NMI) for early warning of a power failure. A preci-
sion comparator monitors the voltage level at the IN pin
relative to an on–chip reference generated by an inter-
nal band gap. The IN pin is a high impedance input
allowing for a user–defined sense point. An external
resistor voltage divider network (Figure 5) is used to
interface with high voltage signals. This sense point
may be derived from a regulated supply or from a higher
DC voltage level closer to the main system power input.
Since the IN trip point V
TP
is 1.25 volts, the proper val-
ues for R1 and R2 can be determined by the equation as
shown in Figure 5. Proper operation of the
DS1705/DS1706 requires that the voltage at the IN pin
be limited to V
CC
. Therefore, the maximum allowable
voltage at the supply being monitored (V
MAX
) can also
be derived as shown in Figure 5. A simple approach to
solving the equation is to select a value for R2 high
enough to keep power consumption low, and solve for
R1. The flexibility of the IN input pin allows for detection
of power loss at the earliest point in a power supply sys-
tem, maximizing the amount of time for system shut–
down between NMI and RST (or RST).
When the supply being monitored decays to the voltage
sense point, the DS1705/DS1706 pulses the NMI out-
put to the active state for a minimum 200
μ
s. The NMI
power fail detection circuitry also has built–in hysteresis
of 100
μ
V. The supply must be below the voltage sense
point for approximately 5
μ
s before a low NMI will be
generated. In this way, power supply noise is removed
from the monitoring function, preventing false inter-
rupts. During a power–up, any detected IN pin levels
below V
TP
by the comparator are disabled from gener-
ating an interrupt until V
CC
rises to V
CCTP
. As a result,
any potential NMI pulse will not be initiated until V
CC
reaches V
CCTP
.
Connecting NMI to PBRST would allow non–maskable
interrupt to generate an automatic reset when an out–
of–tolerance condition occurred in a monitored supply.
An example is shown in Figure 3.
Watchdog Timer
The watchdog timer function forces WDS signals active
when the ST input is not clocked within the 1 second
time out period. Timeout of the watchdog starts when
RST (or RST) becomes inactive. If a high–to–low transi-
tion occurs on the ST input pin prior to time–out, the
watchdog timer is reset and begins to time–out again. If
the watchdog timer is allowed to time out, the WDS sig-
nal is driven active (low) for a minimum of 130 ms. The
ST input can be derived from many microprocessor out-
puts. The typical signals used are the microprocessors
address signals, data signals, or control signals. When
the microprocessor functions normally, these signals
would, as a matter of routine, cause the watchdog to be
reset prior to time–out. To guarantee that the watchdog
timer does not time–out, a high–to–low transition must
occur at or less than the minimum watchdog time–out of
1 second. A typical circuit example is shown in Figure 6.
相關(guān)PDF資料
PDF描述
DS1706R 3.3 and 5.0 Volt MicroMonitor
DS1706S 3.3 and 5.0 Volt MicroMonitor
DS1706T 3.3 and 5.0 Volt MicroMonitor
DS1707 3.3 and 5.0 Volt MicroMonitor
DS1708 3.3 and 5.0 Volt MicroMonitor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS1706PEPA 功能描述:監(jiān)控電路 3.3/5V MicroMonitor RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲(典型值):10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
DS1706PEPA+ 功能描述:監(jiān)控電路 3.3/5V MicroMonitor RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲(典型值):10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
DS1706PESA 功能描述:監(jiān)控電路 3.3/5V MicroMonitor RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲(典型值):10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
DS1706PESA/T&R 制造商:Maxim Integrated Products 功能描述:MAX706P 3.3V 20% ACT.HI 8P SOIC T&R - Tape and Reel
DS1706PESA/T&R 功能描述:電壓監(jiān)測器/監(jiān)控器 RoHS:否 制造商:Texas Instruments 監(jiān)測電壓數(shù):2 監(jiān)測電壓:Adjustable 輸出類型:Open Drain 欠電壓閾值: 過電壓閾值: 準(zhǔn)確性:1 % 工作電源電壓:1.5 V to 6.5 V 工作電源電流:1.8 uA 最大工作溫度:+ 125 C 封裝 / 箱體:SON-6 安裝風(fēng)格:SMD/SMT