參數(shù)資料
型號(hào): DS1689
廠商: DALLAS SEMICONDUCTOR
元件分類: Timer or RTC
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDIP28
封裝: 0.600 INCH, DIP-28
文件頁數(shù): 27/32頁
文件大?。?/td> 376K
代理商: DS1689
DS1689/DS1693
4 of 32
SQW (Square Wave Output) - The SQW pin can output a signal from one of 13 taps provided by the 15
internal divider stages of the real time clock. The frequency of the SQW pin can be changed by
programming Register A as shown in Table 2. The SQW signal can be turned on and off using the SQWE
bit in Register B. A 32 kHz SQW signal is output when SQWE=1, the Enable 32 kHz (E32K) bit in
extended register 04BH is a logic 1, and VCC is above VPF. A 32 kHz square wave is also available when
VCC is less than VPF if E32K=1, ABE=1, and voltage is applied to VBAUX.
AD0-AD7 (Multiplexed Bidirectional Address/Data Bus) - Multiplexed buses save pins because
address information and data information time-share the same signal paths. The addresses are present
during the first portion of the bus cycle and the same pins and signal paths are used for data in the second
portion of the cycle. Address/data multiplexing does not slow the access time of the DS1689 since the bus
change from address to data occurs during the internal RAM access time. Addresses must be valid prior
to the latter portion of ALE, at which time the DS1689/DS1693 latches the address. Valid write data must
be present and held stable during the latter portion of the WR pulse. In a read cycle the DS1689/DS1693
outputs 8 bits of data during the latter portion of the RD pulse. The read cycle is terminated and the bus
returns to a high impedance state as RD transitions high. The address/data bus also serves as a
bidirectional data path for the external extended RAM.
ALE (RTC Address Strobe Input; active high) - A pulse on the address strobe pin serves to
demultiplex the bus. The falling edge of ALE causes the RTC address to be latched within the
DS1689/DS1693.
RD
(RTC Read Input; active low) - RD identifies the time period when the DS1689/DS1693 drives the
bus with RTC read data. The RD signal is an enable signal for the output buffers of the clock.
WR
(RTC Write Input; active low) - The WR signal is an active low signal. The WR signal defines
the time period during which data is written to the addressed register.
CS
(RTC Chip Select Input; active low) - The Chip Select signal must be asserted low during a bus
cycle for the RTC portion of the DS1689/DS1693 to be accessed. CS must be kept in the active state
during RD and WR timing. Bus cycles which take place with ALE asserted but without asserting CS will
latch addresses. However, no data transfer will occur.
IRQ
(Interrupt Request Output; open drain, active low) - The IRQ pin is an active low output of the
DS1689/DS1693 that can be tied to the interrupt input of a processor. The IRQ output remains low as
long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. To
clear the IRQ pin, the application software must clear all enabled flag bits contributing to IRQ ’s active
state.
When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple
interrupting devices can be connected to an IRQ bus. The IRQ pin is an open drain output and requires an
external pull-up resistor.
CEI
(RAM Chip Enable Input; active low) - CEI should be driven low to enable the external RAM.
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