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參數(shù)資料
| 型號： | DS1678S/T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 20/25頁 |
| 文件大小： | 0K |
| 描述： | IC RECORDER REALTIME EVENT 8SOIC |
| 標準包裝： | 2,000 |
| 類型： | 時間事件記錄器 |
| 特點： | 警報器，閏年，NVSRAM，Y2K |
| 存儲容量： | 32B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.6 V ~ 3.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
DS1678 Real-Time Event Recorder
4 of 25
Note 1:
Limits at -40
C are guaranteed by design and not production tested.
Note 2:
All voltages referenced to ground.
Note 3:
After this period, the first clock pulse is generated.
Note 4:
A device must initially provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of the falling edge
of SCL. The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 5:
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL
line is released.
Note 6:
CB—Total capacitance of one bus line in pF.
Note 7:
tR and tF are measured with a 1.7k pullup resistor, 200pF pullup capacitor, 1.7k pulldown resistor, and 5pF
pulldown capacitor.
I
2C COMMUNICATION TIMING DIAGRAM
SU:STO
t
HD:STA
t
t SU:STA
SU:DAT
t
tHIGH
R
t
tLOW
tHD:STA
SCL
START
SDA
STOP
tBUF
tF
REPEATED
START
tHD:DAT
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