參數(shù)資料
型號: DS1677E
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Timer or RTC
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO20
封裝: 4.40 MM, TSSOP-20
文件頁數(shù): 15/18頁
文件大?。?/td> 224K
代理商: DS1677E
DS1677
6 of 18
TIME OF DAY ALARM BITS Table 1
ALARM REGISTER MASK BITS (BIT 7)
SECONDS
MINUTES
HOURS
DAYS
DESCRIPTION
1
Alarm once per second.
0
1
Alarm when seconds match.
0
1
Alarm when minutes and seconds match.
0
1
Alarm when hours, minutes and seconds match.
0
Alarm when day, hours, minutes and seconds match.
SPECIAL PURPOSE REGISTERS
The DS1677 has two additional registers (control register and status register) that control the RTC and
interrupts.
CONTROL REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
EOSC
WP
AIS1
AIS0
0
AIE
EOSC (Enable Oscillator). This bit, when set to logic 0 will start the oscillator. When this bit is set to a
logic 1, the oscillator is stopped and the DS1677 is placed into a low-power standby mode with a current
drain of less than 200nA when in battery-backup mode. When the DS1677 is powered by VCC, the
oscillator is always on regardless of the status of the EOSC bit; however, the RTC is incremented only
when EOSC is a logic 0.
WP (Write Protect). Before any write operation to the real time clock or any other registers, this bit
must be logic 0. When high, the write protect bit prevents a write operation to any register.
AIS0–AIS1 (Analog Input Select). These two bits are used to determine the analog input for the analog-
to-digital conversion. Table 2 lists the specific analog input that is selected by these 2 bits.
AIE (Alarm Interrupt Enable). When set to a logic 1, this bit permits the Interrupt Request Flag (IRQF)
bit in the status register to assert INT. When the AIE bit is set to logic 0, the IRQF bit does not initiate the
INT signal.
ANALOG INPUT SELECTION Table 2
AIS1
AIS0
ANALOG INPUT
0
NONE
0
1
AIN0
1
0
AIN1
1
AIN2
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