參數(shù)資料
型號(hào): DS1677E
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 2/18頁(yè)
文件大?。?/td> 0K
描述: IC CTRLR SYSTEM PORT 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 74
類型: 便攜系統(tǒng)控制器
特點(diǎn): 警報(bào)器,閏年,監(jiān)視計(jì)時(shí)器
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 3 線串口
電源電壓: 4.5 V ~ 5.5 V
電壓 - 電源,電池: 2.5 V ~ 3.7 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
DS1677
10 of 18
CU BIT TIMING Figure 5
3-WIRE SERIAL INTERFACE
Communication with the DS1677 is accomplished through a simple 3-wire interface consisting of the
Chip Select (CS), Serial Clock (SCLK) and Input/Output (I/O) pins.
All data transfers are initiated by driving the CS input high. The CS input serves two functions. First, CS
turns on the control logic, which allows access to the shift register for the address/command sequence.
Second, the CS signal provides a method of terminating either single byte or multiple byte (burst) data
transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data input, data must
be valid during the rising edge of the clock and data bits are output on the falling edge of the clock. If the
CS input goes low, all data transfer terminates and the I/O pin goes to a high impedance state.
Address and data bytes are always shifted LSB first into the I/O pin. Any transaction requires the
address/command byte to specify a read or write to a specific register followed by one or more bytes of
data. The address byte is always the first byte entered after CS is driven high. The most significant bit
( RD /WR) of this byte determines if a read or write will take place. If this bit is 0, one or more read cycles
will occur. If this bit is 1, one or more write cycles will occur.
Data transfers can occur one byte at a time or in multiple byte burst mode. After CS is driven high an
address is written to the DS1677. After the address, one or more data bytes can be read or written. For a
single byte transfer one byte is read or written and then CS is driven low. For a multiple byte transfer,
multiple bytes can be read or written to the DS1677 after the address has been written. Each read or write
cycle causes the register address to automatically increment. Incrementing continues until the device is
disabled. After accessing register 0Eh, the address wraps to 00h.
Data transfer for single byte transfer and multiple byte burst transfer is illustrated in Figures 6 and 7.
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