參數(shù)資料
型號: DS1672S-3
英文描述: Low Voltage Serial Timekeeping Chip
中文描述: 低電壓串行時鐘芯片
文件頁數(shù): 11/13頁
文件大?。?/td> 104K
代理商: DS1672S-3
DS1672
11 of 13
POWER-UP DOWN CHARACTERISTICS
PARAMETER
V
CC
Detect to
RST
(V
CC
Falling)
V
CC
Detect to
RST
(V
CC
Rising)
V
CC
Fall Time; V
PF(MAX)
to V
PF(MIN)
V
CC
Rise Time; V
PF(MIN)
to V
PF(MAX)
(-40
°
C to +85
°
C)
UNITS
μs
ms
μ
s
μ
s
SYMBOL
t
RPD
t
RPU
t
F
t
R
MIN
TYP
MAX
10
NOTES
250
6
300
0
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in write
protection.
NOTES:
1.
All voltages are referenced to ground.
2.
After this period, the first clock pulse is generated.
3.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referenced to the
V
IHMIN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
4.
The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal.
5.
C
B
- total capacitance of one bus line in pF.
6.
If the
EOSC
bit in the Control Register is set to logic 1, t
RPU
is equal to 250 ms plus the start-up time
of the crystal oscillator.
7.
I
CCA
specified with SCL clocking at max frequency (400 kHz).
8.
I
CCS
specified with V
CC
= 3.3V and SDA, SCL=3.3V.
9.
I
CCS
specified with V
CC
= 3.0V and SDA, SCL=3.0V.
10.
I
CCS
specified with V
CC
= 2.0V and SDA, SCL=2.0V.
11.
A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
>= to 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the
next data bit to the SDA line t
R
max + t
SU:DAT
= 1000+250 = 1250 ns before the SCL line is released.
12.
I
OSC
specified with V
CC
= 0V, V
BACKUP
=3.6V and oscillator enabled.
13.
I
BACKUP
specified with V
CC
= 0V, V
BACKUP
=3.6V and oscillator disabled.
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