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DS1672
12 of 12
NOTES:
1.
After this period, the first clock pulse is generated.
2.
A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the
V
IHMIN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
3.
The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal.
4.
C
B
– Total capacitance of one bus line in pF.
5.
If the
EOSC
bit in the control register is set to logic 1, t
RPU
is equal to 250ms plus the start-up time of
the crystal oscillator.
6.
I
CCA
specified with SCL clocking at max frequency (400kHz).
7.
I
CCS
specified with V
CC
= 3.3V and SDA, SCL = 3.3V.
8.
I
CCS
specified with V
CC
= 3.0V and SDA, SCL = 3.0V.
9.
I
CCS
specified with V
CC
= 2.0V and SDA, SCL = 2.0V.
10.
A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
>= to 250ns
must then be met. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the
next data bit to the SDA line t
R
max + t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is released.
11.
I
OSC
specified with V
CC
= 0V, V
BACKUP
= 3.6V and oscillator enabled.
12.
I
BACKUP
specified with V
CC
= 0V, V
BACKUP
= 3.6V and oscillator disabled.
13.
SDA and
RST
.
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