VCC CE OE WE MODE DQ PO" />
參數(shù)資料
型號: DS1646-120+
廠商: Maxim Integrated Products
文件頁數(shù): 7/12頁
文件大小: 0K
描述: IC RAM TIMEKEEP NV 120NS 32-EDIP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 12
類型: 時鐘/日歷
特點: 閏年,NVSRAM
存儲容量: 128KB
時間格式: HH:MM:SS(24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 32-DIP 模塊(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 32-EDIP
包裝: 管件
產(chǎn)品目錄頁面: 1432 (CN2011-ZH PDF)
DS1646/DS1646P
4 of 12
BLOCK DIAGRAM DS1646 Figure 1
TRUTH TABLE DS1646 Table 1
VCC
CE
OE
WE
MODE
DQ
POWER
5V ± 10%
VIH
X
DESELECT
HIGH-Z
STANDBY
X
DESELECT
HIGH-Z
STANDBY
VIL
X
VIL
WRITE
DATA IN
ACTIVE
VIL
VIH
READ
DATA OUT
ACTIVE
VIL
VIH
READ
HIGH-Z
ACTIVE
<4.5V >VBAT
X
DESELECT
HIGH-Z
CMOS STANDBY
<VBAT
X
DESELECT
HIGH-Z
DATA RETENTION
MODE
SETTING THE CLOCK
The MSB Bit, B7, of the control register is the write bit. Setting the write bit to a 1, like the read bit halts
updates to the DS1646 registers. The user can then load them with the correct day, date and time data in
24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters
and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB for the second’s registers. Setting it
to a 1 stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and
the oscillator is running, the LSB of the second’s register will toggle at 512 Hz. When the seconds
register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access
remain valid (i.e., CE low, OE low, and address for seconds register remain valid and stable).
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