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參數(shù)資料
| 型號： | DS1644-120 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Timer or RTC |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, DMA28 |
| 封裝： | MODULE, DIP-28 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 375K |
| 代理商： | DS1644-120 |
DS1644/DS1644P
4 of 11
CLOCK ACCURACY (POWERCAP MODULE)
The DS1644P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within
±1.53 minutes per month (35 ppm) at 25°C.
DS1644 REGISTER MAP - BANK1 Table 2
DATA
ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
FUNCTION
7FFF
-
YEAR
00-99
7FFE
X
-
MONTH
01-12
7FFD
X
-
DATE
01-31
7FFC
X
FT
X
-
DAY
01-07
7FFB
X
-
HOUR
00-23
7FFA
X
-
MINUTES
00-59
7FF9
OSC
-
SECONDS
00-59
7FF8
W
R
X
CONTROL
A
OSC
= STOP BIT
R = READ BIT
FT = FREQUENCY TEST
W
= WRITE BIT
X = UNUSED
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1644 is in the read mode whenever WE (write enable) is high, and CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the
data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA, the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1644 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring high to low transition of WE or CE . The addresses must be held valid
throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of
another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH
afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODE
When VCC is within nominal limits (VCC > 4.5 volts) the DS1644 can be accessed as described above with
read or write cycles. However, when VCC is below the power-fail point VPF (point at which write
protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1644P-120 | 0 TIMER(S), REAL TIME CLOCK, DMA34 |
| DS1644P | 0 TIMER(S), REAL TIME CLOCK, DMA34 |
| DS1644 | 0 TIMER(S), REAL TIME CLOCK, DMA28 |
| DS1646-120 | 0 TIMER(S), REAL TIME CLOCK, DMA32 |
| DS1646P-120 | 0 TIMER(S), REAL TIME CLOCK, DMA34 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1644-120+ | 功能描述:實(shí)時(shí)時(shí)鐘 NV Timekeeping RAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1644-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| DS1644J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad Clock Driver |
| DS1644L-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| DS1644L-120 | 功能描述:實(shí)時(shí)時(shí)鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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