VCC CE CE2 OE WE MODE DQ POWER
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鍨嬭櫉锛� DS1643-70
寤犲晢锛� Maxim Integrated Products
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椤炲瀷锛� 鏅傞悩/鏃ユ
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鎺ュ彛锛� 骞惰伅(li谩n)
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灏佽/澶栨锛� 28-DIP 妯″锛�0.600"锛�15.24mm锛�
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DS1643/DS1643P
4 of 17
Figure 1. Block Diagram
Table 1. Truth Table
VCC
CE
CE2
OE
WE
MODE
DQ
POWER
VIH
X
Deselect
High Z
Standby
X
VIL
X
Deselect
High Z
Standby
VIL
VIH
X
VIL
Write
Data In
Active
VIL
VIH
VIL
VIH
Read
Data Out
Active
5V
10%
VIL
VIH
Read
High-Z
Active
<4.5V >
VBAT
X
Deselect
High-Z
CMOS Standby
<VBAT
X
Deselect
High-Z
Data Retention Mode
SETTING THE CLOCK
The 8-bit of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts updates
to the DS1643 registers. The user can then load them with the correct day, date and time data in 24 hour
BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters and
allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB for the seconds registers. Setting it to
a 1 stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the seconds register will toggle at 512Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512Hz frequency as long as conditions for access remain valid
(i.e., CE low, OE low, CE2 high, and address for seconds register remain valid and stable).
DS1643/
DS1643P
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