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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | DS1603+ |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 8/9闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC COUNTER ELAPSED TIME 5V 7-SIP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 椤炲瀷锛� | 鑰楃敤鏅�(sh铆)闁撹▓(j矛)鏁�(sh霉)鍣� |
| 鏅�(sh铆)闁撴牸寮忥細 | 浜岄€�(j矛n)鍒� |
| 鏁�(sh霉)鎿�(j霉)鏍煎紡锛� | 浜岄€�(j矛n)鍒� |
| 鎺ュ彛锛� | 3 绶氫覆鍙� |
| 闆绘簮闆诲锛� | 4.5 V ~ 5.5 V |
| 闆诲 - 闆绘簮锛岄浕姹狅細 | 3 V ~ 4.5 V |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 閫氬瓟 |
| 灏佽/澶栨锛� | 14-DIP 妯″锛�0.335"锛�8.51mm锛� |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 14-EDIP |
| 鍖呰锛� | 鎵樼洡 |
DS1603
8 of 9
AC ELECTRICAL CHARACTERISTICS
(VCC = +5V 卤10%; 0掳C to +70掳C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Data to CLK Setup
tDC
50
ns
6
CLK to Data Hold
tCDH
60
ns
6
CLK to Data Delay
tCDD
200
ns
6, 7, 8
CLK Low Time
tCL
250
ns
6
CLK High Time
tCH
250
ns
6
CLK Frequency
fCLK
DC
2.0
MHz
6
CLK Rise and Fall
tF, tR
500
ns
RST
to CLK Setup
tCC
100
ns
6
CLK to RST Hold
tCCH
60
ns
6
RST
Inactive Time
tCWH
1
s
6
RST
Low to I/O High-Z
tRDZ
70
ns
6
CLK High to I/O High- Z
tCDZ
20
ns
6
(TA = +25掳C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Expected Data
Retention Time
tDR
10
years
10
NOTES:
1) All voltages are referenced to ground.
2) Logic 1 voltages are specified at a source current of 1mA.
3) Logic 0 voltages are specified at a sink current of 4mA.
4) ICC is specified with the DQ pin open.
5) ICC1 is specified with VCC at 5.0V and RST = GND.
6) Measured at VIH = 2.0V or VIL = 0.8V.
7) Measured at VOH = 2.4V or VOL - 0.4V.
8) Load capacitance = 50pF.
9) Battery trip point is the point at which the VCC powered counter and the serial port stops operation.
The battery trip point drops below the minimum once the internal lithium energy cell is exhausted.
10) The expected tDR is defined as accumulative time in the absence of VCC with the clock oscillator
running.
11) Real-time clock modules can be successfully processed through conventional wave-soldering
techniques as long as temperature exposure to the lithium energy source contained within does not
exceed +85
掳C. Post-solder cleaning with water-washing techniques is acceptable, provided that
ultrasonic vibration is not used.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| DS1642-70+ | IC RAM TIMEKEEP NV 70NS 24-EDIP |
| DS1643P-70+ | IC RAM TIMEKEEP NV 70NS 34-PCM |
| DS1644P-120 | IC RAM TIMEKEEP NV 120NS 34-PCM |
| DS1646-120+ | IC RAM TIMEKEEP NV 120NS 32-EDIP |
| DS1647P-120 | IC RAM TIMEKEEP NV 120NS 34-PCM |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| DS1603+ | 鍔熻兘鎻忚堪:瀵�(sh铆)鏅�(sh铆)鏅�(sh铆)閻� RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅�(sh铆)闁撴牸寮�:HH:MM:SS RTC 瀛樺劜(ch菙)瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube |
| DS1603J | 鍒堕€犲晢:NSC 鍒堕€犲晢鍏ㄧū:National Semiconductor 鍔熻兘鎻忚堪:TRI-STATE Dual Receiver |
| DS1603J/883 | 鍒堕€犲晢:National Semiconductor Corporation 鍔熻兘鎻忚堪:Dual Receiver 14-Pin CDIP |
| DS1603N | 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:Analog Timer Circuit |
| DS16-03P | 鍒堕€犲晢:Cooper Bussmann 鍔熻兘鎻忚堪:TOP SCREW-ON INSERTION BRIDGE, 3 POLE, F - Bulk 鍒堕€犲晢:COOPER BUSSMANN 鍔熻兘鎻忚堪:TOP SCREW-ON INSERTION BRIDGE, 3 POLE, F |
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