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參數(shù)資料
| 型號： | DS1558Y-TRL |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC W/NV RAM 5V 48-TQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，監(jiān)視計時器，Y2K |
| 時間格式： | HH:MM:SS（24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.5 V ~ 3.7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
DS1558
5 of 18
Figure 1. BLOCK DIAGRAM
ES
VCC
Table 1. OPERATING MOD
CE
OE
WE
DQ0–DQ7
MODE
POWER
VIH
X
High-Z
Deselect
Standby
VIL
X
VIL
DIN
Write
Active
VIL
VIH
DOUT
Read
Active
VCC > VPF
VIL
VIH
High-Z
Read
Active
VSO < VCC < VPF
X
High-Z
Deselect
CMOS Standby
VCC < VSO < VPF
X
High-Z
Data Retention
Battery Current
DATA READ MODE
The DS1558 is in the read mode whenever CE is low and WE is high. The device architecture allows
gh access to any valid address location. Valid data is available at the DQ pins within tAA after
the last address input is stable, provided that
ripple-throu
CE
and OE access times are satisfied. If CE or OE access
et, valid data is available at the latter of chip-enable access (tCEA) or at output-enable
(tOEA). The state of the data input/output pins (DQ) is controlled by
times are not m
access time
CE
and OE . If the
ated before tAA, the data lines are driven to an intermediate state until tAA. If the address
inputs are changed while
outputs are activ
CE
and OE remain valid, output data remains valid for output-data hold time
), but then goes indeterminate until the next address access.
(tOH
NOTE: ANY U
S THE RTC.
NUSED UPPER ADDRESS PINS MUST BE CONNECTED TO VCC TO PROPERLY ADDRES
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