(VCC
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� DS1553-100
寤犲晢锛� Maxim Integrated Products
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 6/20闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC RTC RAM Y2K 5V 100NS 28-EDIP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 12
椤�(l猫i)鍨嬶細 鏅�(sh铆)閻�/鏃ユ
鐗归粸(di菐n)锛� 璀﹀牨(b脿o)鍣�锛岄枏骞�锛孨VSRAM锛岀洠(ji膩n)瑕栬▓(j矛)鏅�(sh铆)鍣�锛孻2K
瀛樺劜(ch菙)瀹归噺锛� 8KB
鏅�(sh铆)闁撴牸寮忥細 HH:MM:SS锛�24 灏忔檪(sh铆)锛�
鏁�(sh霉)鎿�(j霉)鏍煎紡锛� YY-MM-DD-dd
鎺ュ彛锛� 骞惰伅(li谩n)
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤�(l猫i)鍨嬶細 閫氬瓟
灏佽/澶栨锛� 28-DIP 妯″锛�0.600"锛�15.24mm锛�
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 28-EDIP
鍖呰锛� 绠′欢
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
14 of 20
WRITE CYCLE, AC CHARACTERISTICS
(VCC = 5.0V 卤10%, TA = Over the operating range.)
85ns ACCESS
100ns ACCESS
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
Write Cycle Time
tWC
85
100
ns
Address Access Time
tAS
0
ns
WE Pulse Width
tWEW
65
70
ns
CE Pulse Width
tCEW
70
75
ns
Data Setup Time
tDS
35
40
ns
Data Hold time
tDH
0
ns
Address Hold Time
tAH
5
ns
WE Data Off Time
tWEZ
30
35
ns
Write Recovery Time
tWR
5
ns
WRITE CYCLE, AC CHARACTERISTICS
(VCC = 3.3V 卤10%, TA = Over the operating range.)
120ns ACCESS
150ns ACCESS
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
Write Cycle Time
tWC
120
150
ns
Address Setup Time
tAS
0
ns
WE Pulse Width
tWEW
100
130
ns
CE Pulse Width
tCEW
110
140
ns
Data Setup Time
tDS
80
90
ns
Data Hold Time
tDH
0
ns
Address Hold Time
tAH
0
ns
WE Data Off Time
tWEZ
40
50
ns
Write Recovery Time
tWR
10
ns
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VE-B1J-MV-F1 CONVERTER MOD DC/DC 36V 150W
VI-BNK-MY-F1 CONVERTER MOD DC/DC 40V 50W
VI-BNJ-MY-F4 CONVERTER MOD DC/DC 36V 50W
VE-B1J-MV CONVERTER MOD DC/DC 36V 150W
VI-BNJ-MY-F2 CONVERTER MOD DC/DC 36V 50W
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
DS1553-100+ 鍔熻兘鎻忚堪:瀵�(sh铆)鏅�(sh铆)鏅�(sh铆)閻� 64kB NV RAM Timekeeper RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅�(sh铆)闁撴牸寮�:HH:MM:SS RTC 瀛樺劜(ch菙)瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube
DS1553-70 鍔熻兘鎻忚堪:瀵�(sh铆)鏅�(sh铆)鏅�(sh铆)閻� RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅�(sh铆)闁撴牸寮�:HH:MM:SS RTC 瀛樺劜(ch菙)瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube
DS1553-70+ 鍔熻兘鎻忚堪:瀵�(sh铆)鏅�(sh铆)鏅�(sh铆)閻� RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅�(sh铆)闁撴牸寮�:HH:MM:SS RTC 瀛樺劜(ch菙)瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube
DS1553-85+ 鍔熻兘鎻忚堪:瀵�(sh铆)鏅�(sh铆)鏅�(sh铆)閻� 64kB NV RAM Timekeeper RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅�(sh铆)闁撴牸寮�:HH:MM:SS RTC 瀛樺劜(ch菙)瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube
DS1553P 鍒堕€犲晢:DALLAS 鍒堕€犲晢鍏ㄧū(ch膿ng):Dallas Semiconductor 鍔熻兘鎻忚堪:64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM