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DS1501/DS1511
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PAB - Power Active Bar Control Bit (0EH bit 4)
When this bit is "0", the PWR pin is in the active low state. When this bit is "1", the PWR pin is in the
high impedance state. This bit can be written to a "1" or "0" by the user. If either TDF AND TPE = "1"
OR KSF = "1", the PAB bit will be cleared to a "0".
TDF - Time of Day/Date Alarm Flag (0EH bit 3)
A "1" in the TDF bit indicates that the current time has matched the alarm time. If the TIE bit is also a
"1", the IRQ pin will go low and a "1" will appear in the IRQF bit.
KSF - Kickstart Flag (0EH bit 2)
This bit is set to a "1" when a kickstart condition occurs or when the user writes it to a "1". This bit is
cleared by writing it to a "0".
WDF - Watchdog Flag (0EH bit 1)
If the processor does not access the DS1501/DS1511 with a write within the period specified in addresses
0CH and 0DH, the WDF bit will be set to a "1". WDF is cleared by writing it to a "0".
IRQF - Interrupt Request Flag (0EH bit 0)
The Interrupt Request Flag (IRQF) bit is set to a "1" when one or more of the following are true:
TDF = TIE = "1"
KSF = KIE = "1"
WDF = WDE = "1"
i.e., IRQF = (TDF TIE) + (KSF KIE) + (WDF WDE)
Any time the IRQF bit is a "1", the IRQ pin is driven low.
TE - Transfer Enable Bit (0FH bit 7)
When the TE bit is a "1", the update transfer functions normally by advancing the counts once per second.
When the TE bit is written to a "0", any update transfer is inhibited and the program can initialize the
time and calendar bytes without an update occurring in the midst of initializing. Read cycles can be
executed in a similar manner. TE is a read/write bit that is not modified by internal functions of the
DS1501/DS1511.
CS - Crystal Select Bit (0FH bit 6)
When CS is set to a "0", the oscillator is configured for operation with a crystal that has a 6 pF specified
load capacitance. When CS="1", the oscillator is configured for a 12.5 pF crystal. CS is disabled in the
DS1511 module and should be set to CS="0".
BME - Burst Mode Enable Bit (0FH bit 5)
The burst mode enable bit allows the extended user RAM address registers to automatically increment for
consecutive reads and writes. When BME is set to a "1", the automatic incrementing will be enabled and
when BME is set to a "0", the automatic incrementing will be disabled.
TPE - Time of Day/Date Alarm Power Enable Bit (0FH bit 4)
The wake up feature is controlled through the TPE bit. When the TDF flag bit is set to a "1", if TPE is a
"1", the PWR pin will be driven active. Therefore, setting TPE to "1" enables the wake up feature.
Writing a "0" to TPE disables the wake up feature.