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參數(shù)資料
| 型號(hào)： | DS1486-150 |
| 英文描述： | RAMified Watchdog Timekeeper |
| 中文描述： | 網(wǎng)狀看門(mén)狗計(jì)時(shí) |
| 文件頁(yè)數(shù)： | 7/17頁(yè) |
| 文件大?。?/td> | 251K |
| 代理商： | DS1486-150 |
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DS1486/DS1486P
7 of 17
TIME OF DAY ALARM MASK BITS
Figure 3
REGISTER
(3) MINUTES
(5) HOURS
1
1
0
1
0
0
0
0
NOTE: ANY OTHER BIT COMBINATIONS OF MASK BIT SETTINGS PRODUCE ILLOGICAL OPERATION.
(7) DAYS
1
1
1
0
ALARM ONCE PER MINUTE
ALARM WHEN MINUTES MATCH
ALARM WHEN HOURS AND MINUTES MATCH
ALARM WHEN HOURS, MINUTES, AND DAYS MATCH
COMMAND REGISTER
Address location 0Bh is the Command Register where mask bits, control bits and flag bits reside. The
operation of each bit is as follows:
TE -
Bit 7 Transfer enable - This bit when set to a logic 0 will disable the transfer of data between
internal and external clock registers. The contents in the external clock registers are now frozen and reads
or writes will not be affected with updates. This bit must be set to a logic 1 to allow updates.
IPSW -
Bit 6 Interrupt switch - When set to a logic 1,
INTA
is the Time of Day Alarm and INTB/(
INTB
)
is the Watchdog Alarm. When set to logic 0, this bit reverses the output pins.
INTA
is now the Watchdog
Alarm output and INTB/(
INTB
) is the Time of Day Alarm output. The
INTA
/SQW output pin shares both
the interrupt A and square wave output function.
INTA
and the square wave function should never be
simultaneously enabled or a conflict may occur (32-pin DIP module only).
IBH/LO -
Bit 5 Interrupt B Sink or Source Current - When this bit is set to a logic 1 and V
CC
is applied,
INTB/(
INTB
) will source current (see DC characteristics IOH). When this bit is set to a logic 0, INTB
will sink current (see DC characteristics IOL).
PU/LVL -
Bit 4 Interrupt pulse mode or level mode - This bit determines whether both interrupts will
output a pulse or level signal. When set to a logic 0,
INTA
and INTB/(
INTB
) will be in the level mode.
When this bit is set to a logic 1, the pulse mode is selected and
INTA
will sink current for a minimum of
3 ms and then release. INTB/(
INTB
) will either sink or source current, depending on the condition of Bit
5, for a minimum of 3 ms and then release. INTB will only source current when there is a voltage present
on V
CC
.
WAM -
Bit 3 Watchdog Alarm Mask - When this bit is set to a logic 0, the Watchdog Interrupt output
will be activated. The activated state is determined by bits 1,4,5, and 6 of the COMMAND REGISTER.
When this bit is set to a logic 1, the Watchdog interrupt output is deactivated.
TDM -
Bit 2 Time of Day Alarm Mask - When this bit is set to a logic 0, the Time of Day Alarm
Interrupt output will be activated. The activated state is determined by bits 0, 4, 5, and 6 of the
COMMAND REGISTER. When this bit is set to a logic 1, the Time of Day Alarm interrupt output is
deactivated.
WAF -
Bit 1 Watchdog Alarm Flag - This bit is set to a logic 1 when a watchdog alarm interrupt occurs.
This bit is read only.
The bit is reset when any of the Watchdog Alarm registers are accessed.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1486P | 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:RAMified Watchdog Timekeeper |
| DS1486P-120 | 功能描述:實(shí)時(shí)時(shí)鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1486P-120+ | 功能描述:實(shí)時(shí)時(shí)鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1486P-150 | 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:RAMified Watchdog Timekeeper |
| DS1487 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Low Power RS-485 1⁄4 Unit Load Multipoint Transceiver |
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