參數(shù)資料
型號(hào): DS1410E
英文描述: Parallel Port Adapter
中文描述: 并口適配器
文件頁(yè)數(shù): 5/7頁(yè)
文件大?。?/td> 126K
代理商: DS1410E
DS1410E
5 of 7
021798
HOST INTERFACE TIMING DIAGRAMS
Figure 3 (cont’d)
t
PDH
= 2
μ
s (TYPICAL)
t
BLR
= 960
μ
s (MINIMUM) (OD = 0
t
BLB
= 96
μ
s (MINIMUM) (OD = 1)
1- WIRE RESET
DESCRIPTION
PIN
I/O
Input pin
14
(ENI
)
I
Chip enable, driven low to begin 1-Wire I/O.
Input pin 11
(O1/
BSY1
)
O
Driven low during time slot (to indicate a DS1481 busy condition). Set to state
of I1 after time slot has finished. (O1/
BSY1
) will go low after D/
CLK
goes low
if sample of I/O communication was low. Returns to state I1 when
ENI
goes
back high (see Figure).
Driven low during time slot (to indicate a DS1481 busy condition). Set to state
of 12 after time slot has finished. O2/
BSY2
will go low after D/
CLK
goes low
if sample of I/O communication was low. Returns to state of 12 when
ENI
goes back high (see Figure).
Data/Clock pin. Used to specify type of time slot before communication
begins. After the time slot has been completed this pin is driven low in order to
solicit the result of the time slot.
Set low (before
ENI
is driven low) to specify that a reset pulse should be
generated on the I/O pin.
Input pin 13
(O2/
BSY2
)
O
Input pin 2
(
D/CLK )
I
Input pin 3
(
RES
)
I
Output Pin 11
(I1)
I
Can be connected to the O1/
BSY1
of another DS1481. May also be connected
to a parallel port printer’s BUSY signal. Internally pulled high via a weak
resistor.
Can be connected to the O2/
BSY2
of another DS1481. Can also be connected
to a parallel port printer SELECT OUT signal. Internally pulled high via a
weak resistor
Set to
ENI
if not the last part on port. Open drain output with weak internal
pullup resistor.
1-Wire I/O line. Bi-directional line with open drain output.
Output Pin 13
(I2)
I
Output Pin 14
(
ENO
)
I/O
O
I/O
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