參數(shù)資料
型號: DS1393U-18+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 9/26頁
文件大?。?/td> 0K
描述: IC RTC W/CHARGER 10-USOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 3,000
類型: 時鐘/日歷
特點: 警報器,閏年,方波輸出,涓流充電器
時間格式: HH:MM:SS:hh(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 3 線串口
電源電壓: 1.71 V ~ 1.89 V
電壓 - 電源,電池: 1.3 V ~ 3.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應商設(shè)備封裝: 10-µMAX
包裝: 帶卷 (TR)
DS1390–DS1394
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
17
Maxim Integrated
Bit 7: Enable Oscillator (
EOSC). When set to logic 0,
this bit starts the oscillator. When this bit is set to logic
1, the oscillator is stopped whenever the device is pow-
ered by VBACKUP. The oscillator is always enabled
when VCC is valid. This bit is enabled (logic 0) when
VCC is first applied.
Bit 5: Battery-Backed Square-Wave and Interrupt
Enable (BBSQI). This bit when set to logic 1 enables the
square wave or interrupt output when VCC is absent and
the DS1390/DS1392/DS1393/DS1394 are being pow-
ered by the VBACKUP pin. When BBSQI is logic 0, the
SQW/INT pin (or SQW and INT pins) goes high imped-
ance when VCC falls below the power-fail trip point. This
bit is disabled (logic 0) when power is first applied.
Bits 4 and 3: Rate Select (RS2 and RS1). These bits
control the frequency of the square-wave output when
the square wave has been enabled. The table below
shows the square-wave frequencies that can be select-
ed with the RS bits. These bits are both set to logic 1
(32kHz) when power is first applied.
Bit 2: Interrupt Control (INTCN). This bit controls the
SQW/INT signal. When the INTCN bit is set to logic 0, a
square wave is output on the SQW/INT pin. The oscilla-
tor must also be enabled for the square wave to be out-
put. When the INTCN bit is set to logic 1, a match
between the timekeeping registers and either of the
alarm registers then activates the SQW/INT (provided
the alarm is also enabled). The corresponding alarm
flag is always set, regardless of the state of the INTCN
bit. The INTCN bit is set to logic 0 when power is first
applied.
Bit 0: Alarm Interrupt Enable (AIE). When set to logic
1, this bit permits the alarm flag (AF) bit in the status
register to assert SQW/INT (when INTCN = 1). When
the AIE bit is set to logic 0 or INTCN is set to logic 0,
the AF bit does not initiate the SQW/INT signal. The AIE
bit is disabled (logic 0) when power is first applied.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
EOSC
0
BBSQI
RS2
RS1
INTCN
0
AIE
Control Register (0D/8Dh) (DS1390/DS1393/DS1394 Only)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
EOSC
0X
X
0X
Control Register (0D/8Dh) (DS1391 Only)
RS2
RS1
SQUARE-WAVE OUTPUT FREQUENCY
0
1Hz
0
1
4.096kHz
1
0
8.192kHz
1
32.768kHz
Special-Purpose Registers
The DS1390–DS1394 have three additional registers
(control, status, and trickle charger) that control the
RTC, alarms, square-wave output, and trickle charger.
Control bits used in the DS1390 become general-pur-
pose, battery-backed, nonvolatile SRAM bits in the
DS1391.
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