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參數(shù)資料
| 型號(hào)： | DS1371U+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/15頁 |
| 文件大小： | 0K |
| 描述： | IC BINARY COUNTER 32-BIT 8-USOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 二進(jìn)制計(jì)數(shù)器 |
| 特點(diǎn)： | 警報(bào)器，方波輸出，監(jiān)視計(jì)時(shí)器 |
| 時(shí)間格式： | 二進(jìn)制 |
| 數(shù)據(jù)格式： | 二進(jìn)制 |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 1.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
DS1371
3 of 15
AC ELECTRICAL CHARACTERISTICS
(VCC = 1.7V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 8)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fast mode
100
400
SCL Clock Frequency (Note 9)
fSCL
Standard mode
0
100
kHz
Fast mode
1.3
Bus Free Time Between STOP and
START Conditions
tBUF
Standard mode
4.7
μs
Fast mode
0.6
Hold Time (repeated) START Condition
(Note 10)
tHD:STA
Standard mode
4.0
μs
Fast mode
1.3
Low Period of SCL Clock
tLOW
Standard mode
4.7
μs
Fast mode
0.6
High Period of SCL Clock
tHIGH
Standard mode
4.0
μs
Fast mode
0
0.9
Data Hold Time (Notes 11, 12)
tHD:DAT
Standard mode
0
0.9
μs
Fast mode
100
Data Setup Time (Note 13)
tSU:DAT
Standard mode
250
ns
Fast mode
0.6
Start Setup Time
tSU:STA
Standard mode
4.7
μs
Fast mode
20 +
0.1CB
B
300
Rise Time of Both SDA and SCL
Signals (Note 9)
tR
Standard mode
20 +
0.1CB
B
1000
ns
Fast mode
20 +
0.1CB
B
300
Fall Time of Both SDA and SCL Signals
(Note 9)
tF
Standard mode
20 +
0.1CB
B
300
ns
Fast mode
0.6
Setup Time for STOP Condition
tSU:STO
Standard mode
4.7
μs
Capacitive Load for Each Bus Line
(Note 7)
CB
B
400
pF
Pulse Width of Spikes that Must be
Suppressed by the Input Filter (Note 14)
TSP
Fast mode
30
ns
Watchdog Strobe (WDS) Pulse Width
tWDS
100
ns
Oscillator Stop Flag (OSF) Delay
(Note 8)
tOSF
100
ms
Note 1: All voltages are referenced to ground.
Note 2: SCL and WDS only.
Note 3: SDA and SQW/
INT.
Note 4: Limits at -40
°C are guaranteed by design and not production tested.
Note 5: ICCA—SCL clocking at max frequency = 400kHz. WDS inactive.
Note 6: Specified with WDS input and I
2C bus inactive, SCL = SDA = VCC.
Note 7: Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
Note 8: The parameter tOSF is the period of time the oscillator must be stopped in order for the OSF flag to be set over the voltage range of 1.3V
≤ VCC ≤ VCCMAX.
Note 9: A fast mode device can be used in a standard mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of
the SCL signal, it must output the next data bit to the SDA line tR MAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.
Note 10: After this period, the first clock pulse is generated.
Note 11: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
Note 12: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 13: CB—total capacitance of one bus line in pF.
B
Note 14: This parameter is not production tested.
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| DS1372 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:I2C, 32-Bit, Binary Counter Clock with 64-Bit ID |
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