I2C RTC with Trickle Charger 4 Maxim Integrated DS1340 POWER-UP/POWER-DOWN CHARA" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� DS1340Z-3+T&R
寤犲晢锛� Maxim Integrated Products
鏂囦欢闋佹暩(sh霉)锛� 11/16闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC RTC I2C W/CHARGER 3V 8-SOIC
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 2,500
椤炲瀷锛� 鏅�(sh铆)閻�/鏃ユ
鐗归粸(di菐n)锛� 闁忓勾锛屾柟娉㈣几鍑�锛屾稉娴佸厖闆诲櫒
鏅�(sh铆)闁撴牸寮忥細 HH:MM:SS锛�24 灏忔檪(sh铆)锛�
鏁�(sh霉)鎿�(j霉)鏍煎紡锛� YY-MM-DD-dd
鎺ュ彛锛� I²C锛�2 绶氫覆鍙�
闆绘簮闆诲锛� 2.7 V ~ 5.5 V
闆诲 - 闆绘簮锛岄浕姹狅細 1.3 V ~ 3.7 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-SOIC
鍖呰锛� 甯跺嵎 (TR)
I2C RTC with Trickle Charger
4
Maxim Integrated
DS1340
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40掳C to +85掳C) (Figure 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Recovery at Power-Up
tREC
(Note 17)
2
ms
VCC Fall Time; VPF(MAX) to
VPF(MIN)
tVCCF
300
s
VCC Rise Time; VPF(MIN) to
VPF(MAX)
tVCCR
0s
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode.
Note 1:
Limits at -40掳C are guaranteed by design and not production tested.
Note 2:
All voltages are referenced to ground.
Note 3:
Measured at VCC = typ, VBACKUP = 0V, register 08h = A5h.
Note 4:
The use of the 250
惟 trickle-charge resistor is not allowed at VCC > 3.63V and should not be enabled.
Note 5:
Measured at VCC = typ, VBACKUP = 0V, register 08h = A6h.
Note 6:
Measured at VCC = typ, VBACKUP = 0V, register 08h = A7h.
Note 7:
ICCA鈥擲CL clocking at max frequency = 400kHz.
Note 8:
Specified with I2C bus inactive.
Note 9:
Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
Note 10:
Limits at +25掳C are guaranteed by design and not production tested.
Note 11:
After this period, the first clock pulse is generated.
Note 12:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH(MIN) of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
Note 13:
The maximum tHD:DAT only has to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 14:
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT
鈮� to 250ns must be met. This
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line tR MAX + tSU:DAT = 1000 + 250 = 1250ns
before the SCL line is released.
Note 15:
CB鈥攖otal capacitance of one bus line in pF.
Note 16:
The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the 0V
鈮� VCC 鈮�
VCCMAX and 1.3V
鈮� VBAT 鈮�3.7V range.
Note 17:
This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay
occurs.
SCL
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
SDA
STOP
START
REPEATED
START
tBUF
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHD:STA
tSP
tSU:STA
tHIGH
tR
tF
tLOW
Figure 1. Data Transfer on I2C Serial Bus
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