I2C RTC with Trickle Charger 12 Maxim Integrated DS1340 determined by the master" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� DS1340Z-3+
寤犲晢锛� Maxim Integrated Products
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 4/16闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC RTC I2C W/CHARGER 3V 8-SOIC
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 100
椤�(l猫i)鍨嬶細 鏅�(sh铆)閻�/鏃ユ
鐗归粸(di菐n)锛� 闁忓勾锛屾柟娉㈣几鍑�锛屾稉娴佸厖闆诲櫒
鏅�(sh铆)闁撴牸寮忥細 HH:MM:SS锛�24 灏忔檪(sh铆)锛�
鏁�(sh霉)鎿�(j霉)鏍煎紡锛� YY-MM-DD-dd
鎺ュ彛锛� I²C锛�2 绶氫覆鍙�
闆绘簮闆诲锛� 2.7 V ~ 5.5 V
闆诲 - 闆绘簮锛岄浕姹狅細 1.3 V ~ 3.7 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-SOIC
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 1433 (CN2011-ZH PDF)
I2C RTC with Trickle Charger
12
Maxim Integrated
DS1340
determined by the master device. The information
is transferred byte-wise and each receiver
acknowledges with a ninth bit.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowl-
edge after the reception of each byte. The master
device must generate an extra clock pulse that is
associated with this acknowledge bit.
A device that acknowledges must pull down the
SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable low during
the high period of the acknowledge-related clock
pulse. Setup and hold times must be taken into
account. A master must signal an end of data to
the slave by not generating an acknowledge bit on
the last byte that has been clocked out of the
slave. In this case, the slave must leave the data
line high to enable the master to generate the
STOP condition.
Figures 8 and 9 detail how data transfer is accom-
plished on the I2C bus. Depending upon the state of
the R/W bit, two types of data transfer are possible:
Data transfer from a master transmitter to a
slave receiver. The first byte transmitted by the
master is the slave address. Next follows a num-
ber of data bytes. The slave returns an acknowl-
edge bit after each received byte.
Data transfer from a slave transmitter to a mas-
ter receiver. The master transmits the first byte (the
slave address). The slave then returns an acknowl-
edge bit. Next follows a number of data bytes trans-
mitted by the slave to the master. The master
returns an acknowledge bit after all received bytes
other than the last byte. At the end of the last
received byte, a not acknowledge is returned.
The master device generates all the serial clock
pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a
repeated START condition. Since a repeated
START condition is also the beginning of the next
serial transfer, the bus is not released.
The DS1340 can operate in the following two modes:
Slave Receiver Mode (Write Mode): Serial data
and clock are received through SDA and SCL.
After each byte is received, an acknowledge bit is
transmitted. Start and STOP conditions are recog-
nized as the beginning and end of a serial trans-
fer. Hardware performs address recognition after
reception of the slave address and direction bit.
The slave address byte is the first byte received
after the master generates the START condition.
The slave address byte contains the 7-bit DS1340
address, which is 1101000, followed by the direc-
tion bit (R/W), which is 0 for a write. After receiving
and decoding the slave address byte, the DS1340
outputs an acknowledge on SDA. After the
DS1340 acknowledges the slave address + write
bit, the master transmits a word address to the
DS1340. This sets the register pointer on the
DS1340, with the DS1340 acknowledging the
transfer. The master can then transmit zero or
more bytes of data, with the DS1340 acknowledg-
ing each byte received. The register pointer incre-
ments after each data byte is transferred. The
master generates a STOP condition to terminate
the data write.
Slave Transmitter Mode (Read Mode): The first
byte is received and handled as in the slave
receiver mode. However, in this mode, the direc-
tion bit indicates that the transfer direction is
reversed. The DS1340 transmits serial data on
SDA while the serial clock is input on SCL. Start
and STOP conditions are recognized as the begin-
ning and end of a serial transfer. Hardware per-
forms address recognition after reception of the
slave address and direction bit. The slave address
byte is the first byte received after the master gen-
erates the START condition. The slave address
byte contains the 7-bit DS1340 address, which is
1101000, followed by the direction bit (R/W),
which is 1 for a read. After receiving and decoding
the slave address byte, the DS1340 outputs an
acknowledge on SDA. The DS1340 then begins to
transmit data starting with the register address
pointed to by the register pointer. If the register
pointer is not written to before the initiation of a
read mode, the first address that is read is the last
one stored in the register pointer. The DS1340
must receive a not acknowledge to end a read.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
MCP4024T-502E/OT IC DGTL POT 5K 1CH SOT23-5
VI-B23-MW-B1 CONVERTER MOD DC/DC 24V 100W
M83723/75R2016N CONN PLUG 16POS STRAIGHT W/SCKT
DS1338Z-3+ IC RTC 56BYTE NV RAM 3V 8-SOIC
VI-B22-MW-B1 CONVERTER MOD DC/DC 15V 100W
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
DS1340Z-3/T&R 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:REAL TIME CLOCK SERL 8SOIC - Tape and Reel
DS1340Z-3+ 鍔熻兘鎻忚堪:瀵�(sh铆)鏅�(sh铆)鏅�(sh铆)閻� I2C RTC w/Trickle Charger RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅�(sh铆)闁撴牸寮�:HH:MM:SS RTC 瀛樺劜(ch菙)瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube
DS1340Z-3+T&R 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:REAL TIME CLOCK SERL 8SOIC - Tape and Reel 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:IC RTC I2C W/CHARGER 3V 8-SOIC 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:Real Time Clock I2C RTC w/Trickle Charger
DS1340Z-3+T&R 鍔熻兘鎻忚堪:瀵�(sh铆)鏅�(sh铆)鏅�(sh铆)閻� I2C RTC w/Trickle Charger RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅�(sh铆)闁撴牸寮�:HH:MM:SS RTC 瀛樺劜(ch菙)瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube
DS1340Z-33 鍔熻兘鎻忚堪:瀵�(sh铆)鏅�(sh铆)鏅�(sh铆)閻� RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅�(sh铆)闁撴牸寮�:HH:MM:SS RTC 瀛樺劜(ch菙)瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube