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參數(shù)資料
| 型號： | DS1338Z-33+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC 56BYTE NV RAM 3.3V 8SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 類型： | 時鐘/日歷 |
| 特點： | 閏年，NVSRAM，方波輸出 |
| 存儲容量： | 56B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 3 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.3 V ~ 3.7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 標準包裝 |
| 其它名稱： | DS1338Z-33+T&RDKR |
DS1338 I2C RTC with 56-Byte NV RAM
12 of 16
I2C SERIAL DATA BUS
The DS1338 supports the I2C protocol. A device that sends data onto the bus is defined as a transmitter and a
device receiving data is a receiver. The device that controls the message is called a master. The devices that are
controlled by the master are referred to as slaves. The bus must be controlled by a master device, which generates
the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1338
operates as a slave on the I2C bus. Within the bus specifications, a standard mode (100kHz maximum clock rate)
and a fast mode (400kHz maximum clock rate) are defined. The DS1338 works in both modes. Connections to the
bus are made through the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (Figure 5).
Data transfer can be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines
the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable
for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions is not limited and is determined by the master device. The
information is transferred byte-wise and each receiver acknowledges with a ninth bit.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception
of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that
the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and
hold times must be taken into account. A master must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data
line HIGH to enable the master to generate the STOP condition.
Figure 5. Data Transfer on I2C Serial Bus
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1339 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:I2C Serial Real-Time Clock |
| DS1339_06 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:I2C Serial Real-Time Clock |
| DS1339_11 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:I2C Serial Real-Time Clock Trickle-Charge Capability |
| DS1339A | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Low-Current, I2C, Serial Real-Time Clock |
| DS1339A_13 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Low-Current, I2C, Serial Real-Time Clock |
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