DS1338 I2C RTC with 56-Byte NV RAM 4 of 16 POWER-UP/POWER-DOWN CHARACTERISTICS <" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� DS1338U-3+T&R
寤犲晢锛� Maxim Integrated Products
鏂囦欢闋佹暩(sh霉)锛� 11/16闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC RTC 56BYTE NV RAM 3V 8-USOP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 3,000
椤炲瀷锛� 鏅�(sh铆)閻�/鏃ユ
鐗归粸(di菐n)锛� 闁忓勾锛孨VSRAM锛屾柟娉㈣几鍑�
瀛樺劜(ch菙)瀹归噺锛� 56B
鏅�(sh铆)闁撴牸寮忥細 HH:MM:SS锛�12/24 灏忔檪(sh铆)锛�
鏁�(sh霉)鎿�(j霉)鏍煎紡锛� YY-MM-DD-dd
鎺ュ彛锛� I²C锛�2 绶氫覆鍙�
闆绘簮闆诲锛� 2.7 V ~ 5.5 V
闆诲 - 闆绘簮锛岄浕姹狅細 1.3 V ~ 3.7 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-uMAX
鍖呰锛� 甯跺嵎 (TR)
DS1338 I2C RTC with 56-Byte NV RAM
4 of 16
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40掳C to +85掳C) (Note 1, Figure 1)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Recovery at Power-Up (Note 15)
tREC
2
ms
VCC Fall Time; VPF(MAX) to VPF(MIN)
tVCCF
300
s
VCC Rise Time; VPF(MIN) to VPF(MAX)
tVCCR
0
s
Warning: Negative undershoots below -0.3V while the part is in battery-backed mode may cause
loss of data.
Note 1:
Limits at -40掳C are guaranteed by design and not production tested.
Note 2:
All voltages are referenced to ground.
Note 3:
SCL only.
Note 4:
SDA and SQW/OUT.
Note 5:
ICCA鈥擲CL clocking at max frequency = 400kHz.
Note 6:
Specified with the I2C bus inactive.
Note 7:
Measured with a 32.768kHz crystal attached to X1 and X2.
Note 8:
After this period, the first clock pulse is generated.
Note 9:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 10:
The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 11:
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT 鈮� to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line
is released.
Note 12:
CB鈥攖otal capacitance of one bus line in pF.
Note 13:
Guaranteed by design. Not production tested.
Note 14:
The parameter tOSF is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of
0.0V 鈮� VCC 鈮� VCC(MAX) and 1.3V 鈮� VBAT 鈮� 3.7V.
Note 15:
This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay occurs.
Figure 1. Power-Up/Power-Down Timing
OUTPUTS
VCC
VPF(MAX)
VPF(MIN)
INPUTS
HIGH-Z
DON'T CARE
VALID
RECOGNIZED
VALID
tVCCF
tVCCR
tREC
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