4. ICCO" />
參數(shù)資料
型號: DS1314S-2/T&R
廠商: Maxim Integrated
文件頁數(shù): 2/12頁
文件大?。?/td> 0K
描述: IC CTRLR NV W/BATT MON 3V 8-SOIC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
控制器類型: 非易失性 RAM
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
DS1314
10 of 12
NOTES:
2. All voltages referenced to ground.
3. Measured with outputs open circuited.
4. ICCO1 is the maximum average load which the DS1314 can supply to attached memories at VCCO
VCCI -0.2V.
5. ICCO1 is the maximum average load which the DS1314 can supply to attached memories at VCCO
VCCI -0.3V.
6. All inputs within 0.3V of ground or VCCI.
7. ICCO2 is the maximum average load current which the DS1314 can supply to the memories in the
battery-backup mode.
8. Measured with a load as shown in Figure 2.
9. Chip Enable Output ( CEO ) can only sustain leakage current in the battery-backup mode.
10. CEO will be held high for a time equal to tREC after VCCI crosses VCCTP on power-up.
11. BW and RST are open drain outputs and as such cannot source current. External pull-up resistors
should be connected to these pins for proper operation. Both BW and RST can sink 10 mA.
12. tCE maximum must be met to ensure data integrity on power-down.
13. In battery-backup mode, inputs must never be below ground or above VCCO.
DC TEST CONDITIONS
Outputs Open
All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: See below
Input Pulse Levels: 0 - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5 ns
OUTPUT LOAD Figure 2
* INCLUDING SCOPE AND JIG CAPACITANCE
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