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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | DS1302Z/T&R |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 8/13闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC TIMEKEEPER T-CHARGE 8-SOIC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,500 |
| 椤�(l猫i)鍨嬶細 | 鏅�(sh铆)閻�/鏃ユ |
| 鐗归粸(di菐n)锛� | 闁忓勾锛孨VSRAM锛屾稉娴佸厖闆诲櫒 |
| 瀛樺劜(ch菙)瀹归噺锛� | 31B |
| 鏅�(sh铆)闁撴牸寮忥細 | HH:MM:SS锛�12/24 灏忔檪(sh铆)锛� |
| 鏁�(sh霉)鎿�(j霉)鏍煎紡锛� | YY-MM-DD-dd |
| 鎺ュ彛锛� | 3 绶�(xi脿n)涓插彛 |
| 闆绘簮闆诲锛� | 2 V ~ 5.5 V |
| 闆诲 - 闆绘簮锛岄浕姹狅細 | 2 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤�(l猫i)鍨嬶細 | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-SOIC |
| 鍖呰锛� | 甯跺嵎 (TR) |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)鐣�(d膩ng)鍓嶇8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)
DS1302 Trickle-Charge Timekeeping Chip
4 of 13
PIN DESCRIPTION
PIN
NAME
FUNCTION
1
VCC2
Primary Power-Supply Pin in Dual Supply Configuration. VCC1 is connected to a
backup source to maintain the time and date in the absence of primary power. The
DS1302 operates from the larger of VCC1 or VCC2. When VCC2 is greater than VCC1 +
0.2V, VCC2 powers the DS1302. When VCC2 is less than VCC1, VCC1 powers the
DS1302.
2
X1
3
X2
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator is
designed for operation with a crystal having a specified load capacitance of 6pF.
For more information on crystal selection and crystal layout considerations, refer to
Application Note 58: Crystal Considerations for Dallas Real-Time Clocks. The
DS1302 can also be driven by an external 32.768kHz oscillator. In this
configuration, the X1 pin is connected to the external oscillator signal and the X2 pin
is floated.
4
GND
Ground
5
CE
Input. CE signal must be asserted high during a read or a write. This pin has an
internal 40k
惟 (typ) pulldown resistor to ground. Note: Previous data sheet revisions
referred to CE as
RST. The functionality of the pin has not changed.
6
I/O
Input/Push-Pull Output. The I/O pin is the bidirectional data pin for the 3-wire
interface. This pin has an internal 40k
惟 (typ) pulldown resistor to ground.
7
SCLK
Input. SCLK is used to synchronize data movement on the serial interface. This pin
has an internal 40k
惟 (typ) pulldown resistor to ground.
8
VCC1
Low-Power Operation in Single Supply and Battery-Operated Systems and Low-
Power Battery Backup. In systems using the trickle charger, the rechargeable
energy source is connected to this pin. UL recognized to ensure against reverse
charging current when used with a lithium battery. Go to
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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| VI-JN4-MZ | CONVERTER MOD DC/DC 48V 25W |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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| DS1304FP000 | 鍒堕€犲晢:Thomas & Betts 鍔熻兘鎻忚堪:100A,CON,3P4W,MG,304,277/480V |
| DS1304MP000 | 鍒堕€犲晢:Thomas & Betts 鍔熻兘鎻忚堪:100A,PLG,3P4W,MG,304,277/480V |
| DS1304MR000 | 鍒堕€犲晢:Thomas & Betts 鍔熻兘鎻忚堪:100A,NTL,3P4W,MG,304,277/480V |
| DS1304MRAB0 | 鍒堕€犲晢:Thomas & Betts 鍔熻兘鎻忚堪:100A,NLT,3P4W,MG,304,AB0,277/480V |
| DS1305 | 鍔熻兘鎻忚堪:瀵�(sh铆)鏅�(sh铆)鏅�(sh铆)閻� Serial Alarm RTC 3-Wire RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔(xi脿n)鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅�(sh铆)闁撴牸寮�:HH:MM:SS RTC 瀛樺劜(ch菙)瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube |
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