參數(shù)資料
型號(hào): DS1267E-50+T&R
廠(chǎng)商: Maxim Integrated Products
文件頁(yè)數(shù): 7/12頁(yè)
文件大?。?/td> 0K
描述: IC POT DUAL DIGITAL 50K 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
接片: 256
電阻(歐姆): 50k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 750 ppm/°C
存儲(chǔ)器類(lèi)型: 易失
接口: 3 線(xiàn)串口
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
DS1267
4 of 12
102199
STACKED CONFIGURATION
The potentiometers of the DS1267 can be connected in series as shown in Figure 3. This is referred to as
the stacked configuration. The stacked configuration allows the user to double the total end-to-end
resistance of the part and the number of steps to 512 (or 9 bits of resolution).
The wiper output for the combined stacked potentiometer will be taken at the SOUT pin, which is the
multiplexed output of the wiper of potentiometer-0 (W0) or potentiometer-1 (W1). The potentiometer
wiper selected at the SOUT output is governed by the setting of the stack select bit (bit 0) of the 17-bit I/O
shift register. If the stack select bit has value 0, the multiplexed output, SOUT, will be that of the
potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed output, SOUT, will be that of the
potentiometer-1 wiper.
STACKED CONFIGURATION Figure 3
CASCADE OPERATION
A feature of the DS1267 is the ability to control multiple devices from a single processor. Multiple
DS1267s can be linked or daisy-chained as shown in Figure 4. As a data bit is entered into the I/O shift
register of the DS1267 a bit will appear at the COUT output within a maximum delay of 50 nanoseconds.
The stack select bit of the DS1267 will always be the first out the part at the beginning of a transaction.
Additionally the COUT pin is always active regardless of the state of RST . This allows one to read the I/O
shift register without changing its value.
CASCADING MULTIPLE DEVICES Figure 4
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