CC = 5.0V ± 10%) PARAMETER SY" />
參數(shù)資料
型號(hào): DS1267-100+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 12/12頁(yè)
文件大小: 0K
描述: IC POT DUAL DIGITAL 100K 14-DIP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 25
接片: 256
電阻(歐姆): 100k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 750 ppm/°C
存儲(chǔ)器類(lèi)型: 易失
接口: 3 線串口
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 通孔
封裝/外殼: 14-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 14-PDIP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1430 (CN2011-ZH PDF)
DS1267
9 of 12
102199
ANALOG RESISTOR CHARACTERISTICS (-40
°C to +85°C; V
CC = 5.0V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
End-to-End Resistor Tolerance
-20
+20
%
10
Absolute Linearity
±.75
LDB
3
Relative Linearity
±0.3
LDB
4
-3 dB Cutoff Frequency
FCUTOFF
Hz
6
Temperature Coefficient
750
ppm/C
CAPACITANCE
(TA=25
°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
CIN
5
pF
Output Capacitance
COUT
7
pF
AC ELECTRICAL CHARACTERISTICS
(-40
°C to +85°C; V
CC = 5.0V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CLK Frequency
fCLK
DC
10
MHz
8
Width of CLK Pulse
tCH
50
ns
8
Data Setup Time
tDC
30
ns
8
Data Hold Time
tCDH
10
ns
8
Propagation Delay Time Low to
High Level Clock to Output
tPLH
50
ns
8
Propagation Delay Time High to
Low Level
tPHL
50
ns
8
RST
High to Clock Input High
tCC
50
ns
8
RST
Low to Clock Input High
tHLT
50
ns
8
RST
Inactive
tRLT
125
ns
8
CLK Rise Time, CLK Fall Time
tCR
50
ns
8
NOTES:
1. All voltages are referenced to ground.
2. Resistor inputs cannot exceed the substrate bias voltage, Vb, in the negative direction.
3. Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper
position. Device test limits ±1.6 LSB.
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