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參數(shù)資料
型號: DS1251YP-70+
廠商: Maxim Integrated Products
文件頁數(shù): 16/20頁
文件大小: 0K
描述: IC NVSRAM 4MBIT 70NS 34PCM
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 40
類型: Phantom 計時芯片
特點: 閏年,NVSRAM
存儲容量: 512KB
時間格式: HH:MM:SS:hh(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 4.5 V ~ 5.5 V
電壓 - 電源,電池: 3V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 34-PowerCap? 模塊
供應商設備封裝: 34-PowerCap 模塊
包裝: 管件
DS1251/DS1251P
5 of 20
from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either
receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other
locations outside the memory block can be interleaved with CE cycles without interrupting the pattern
recognition sequence or data transfer sequence to the phantom clock.
PHANTOM CLOCK REGISTER INFORMATION
The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating
the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.
Data contained in the phantom clock register is in binary-coded decimal format (BCD). Reading and
writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.
PHANTOM CLOCK REGISTER DEFINITION Figure 1
NOTE: THE PATTERN RECOGNITION IN HEX IS C5, 3A, A3, 5C, C5, 3A, A3, 5C. THE ODDS OF THIS PATTERN BEING ACCIDENTALLY
DUPLICATED AND CAUSING INADVERTENT ENTRY TO THE PHANTOM CLOCK IS LESS THAN 1 IN 1019. THIS PATTERN IS SENT TO
THE PHANTOM CLOCK LSB TO MSB.
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