參數資料
型號: DS1244YP-70
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Timer or RTC
英文描述: 0 TIMER(S), REAL TIME CLOCK, DMA34
封裝: POWERCAP MODULE-34
文件頁數: 17/19頁
文件大?。?/td> 351K
代理商: DS1244YP-70
DS1244/DS1244P
7 of 19
Figure 2. PHANTOM CLOCK REGISTER DEFINITION
AM/PM/12/24 MODE
Bit 7 of the hours register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour
mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour
mode, bit 5 is the second 10-hour bit (20–23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the RESET and oscillator functions. Bit 4 controls the
RESET
(pin 1). When the RESET bit is set to logic 1, the RESET input pin is ignored. When the RESET
bit is set to logic 0, a low input on the RESET pin will cause the phantom clock to abort data transfer
without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the
oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These
bits are shipped from the factory set to a logic 1.
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits that always read logic 0. When writing these
locations, either a logic 1 or 0 is acceptable.
相關PDF資料
PDF描述
DS1244WP-120 0 TIMER(S), REAL TIME CLOCK, DMA34
DS1244Y-70 0 TIMER(S), REAL TIME CLOCK, PDMA28
DS1244Y 0 TIMER(S), REAL TIME CLOCK, PDIP28
DS1245AB-100 128K X 8 NON-VOLATILE SRAM MODULE, 100 ns, DMA32
DS1245Y-120 128K X 8 NON-VOLATILE SRAM MODULE, 120 ns, DMA32
相關代理商/技術參數
參數描述
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