參數(shù)資料
型號: DS1230Y-200
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Static RAM
英文描述: 32K X 8 NON-VOLATILE SRAM MODULE, 200 ns, DMA28
封裝: 0.740 INCH, DIP-28
文件頁數(shù): 12/13頁
文件大?。?/td> 237K
代理商: DS1230Y-200
DS1230Y/AB
8 of 13
(tA=25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Expected Data Retention Time
tDR
10
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
WE
is high for a Read Cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDH, tDS are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in high-impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
9. Each DS1230 has a built-in switch that disconnects the lithium source until the user first applies VCC.
The expected tDR is defined as accumulative time in the absence of VCC starting from the time power
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production testing.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0
°C to 70°C. For industrial products (IND), this range is -40°C to
+85
°C.
11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC.
12. tWR1 and tDH1 are measured from WE going high.
13. tWR2 and tDH2 are measured from CE going high.
14. DS1230 modules are recognized by Underwriters Laboratory (U.L.
) under file E99151.
DC TEST CONDITIONS
AC TEST CONDITIONS
Outputs Open
Output Load: 100 pF + 1TTL Gate
Cycle = 200 ns for operating current
Input Pulse Levels: 0 - 3.0V
All voltages are referenced to ground
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5 ns
相關(guān)PDF資料
PDF描述
DS1230Y-120 32K X 8 NON-VOLATILE SRAM MODULE, 120 ns, DMA28
DS1230AB-200 32K X 8 NON-VOLATILE SRAM MODULE, 200 ns, PDIP28
DS1230Y-85 32K X 8 NON-VOLATILE SRAM MODULE, 85 ns, PDIP28
DS1230ABP-100 32K X 8 NON-VOLATILE SRAM MODULE, 100 ns, DMA34
DS1230AB-85 32K X 8 NON-VOLATILE SRAM MODULE, 85 ns, PDIP28
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