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參數(shù)資料
| 型號： | DS1220Y-200 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Static RAM |
| 英文描述： | 2K X 8 NON-VOLATILE SRAM MODULE, 200 ns, PDIP24 |
| 封裝： | 0.720 INCH, EXTENDED, DIP-24 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 144K |
| 代理商： | DS1220Y-200 |
DS1220Y
2 of 8
READ MODE
The DS1220Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 11 address inputs
(A0-A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data
access must be measured from the later-occurring signal and the limiting parameter is either tCO for CE or
tOE for OE rather than address access.
WRITE MODE
The DS1220Y executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write
cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be
kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active)
then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1220Y provides full-functional capability for VCC greater than 4.5 volts and write protects at 4.25
nominal. Data is maintained in the absence of VCC without any additional support circuitry. The
DS1220Y constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write
protects itself, all inputs become “don’t care,” and all outputs become high-impedance. As VCC falls
below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to
retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit
connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can
resume after VCC exceeds 4.5 volts.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1220Y-150 | 2K X 8 NON-VOLATILE SRAM MODULE, 150 ns, PDIP24 |
| DS1220Y | 2K X 8 NON-VOLATILE SRAM MODULE, 200 ns, PDIP24 |
| DS1222S | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO16 |
| DS1222 | SPECIALTY MICROPROCESSOR CIRCUIT, PDIP14 |
| DS1225AB-170 | 8K X 8 NON-VOLATILE SRAM MODULE, 170 ns, DMA28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1220Y-200+ | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1220Y-200-IND | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based) |
| DS1220Y-200IND+ | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1221 | 功能描述:IC CTRLR/DECODER 4BIT 16-DIP RoHS:否 類別:集成電路 (IC) >> 存儲器 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 控制器類型:靜態(tài) RAM（SRAM） 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC W 包裝:管件 |
| DS1221S | 功能描述:IC CTRLR/DECODER 4BIT 16-SOIC RoHS:否 類別:集成電路 (IC) >> 存儲器 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 控制器類型:靜態(tài) RAM（SRAM） 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC W 包裝:管件 |
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