參數(shù)資料
型號(hào): DS1220AB-150
廠商: DALLAS SEMICONDUCTOR
元件分類: Static RAM
英文描述: 2K X 8 NON-VOLATILE SRAM MODULE, 150 ns, PDIP24
封裝: 0.720 INCH, EXTENDED, DIP-24
文件頁數(shù): 7/9頁
文件大?。?/td> 136K
代理商: DS1220AB-150
DS1220AB/AD
7 of 9
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
(tA: See Note 10)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CE at VIH before Power-Down
tPD
0
s
11
VCC slew from VTP to 0v
tF
300
s
VCC slew from 0V to VTP
tR
300
s
CE at VIH after Power-Up
tREC
2
125
ms
(TA =25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Expected Data Retention Time
tDR
10
years
9
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in the
battery backup mode.
NOTES:
1.
WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or CE
going low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output
buffers remain in a high-impedance state during this period.
相關(guān)PDF資料
PDF描述
DS1220AB-100 2K X 8 NON-VOLATILE SRAM MODULE, 100 ns, PDIP24
DS1220AB-120 2K X 8 NON-VOLATILE SRAM MODULE, 120 ns, PDIP24
DS1220AD-100 2K X 8 NON-VOLATILE SRAM MODULE, 100 ns, PDIP24
DS1220AD-120 2K X 8 NON-VOLATILE SRAM MODULE, 120 ns, DMA24
DS1220AD-200 2K X 8 NON-VOLATILE SRAM MODULE, 200 ns, DMA24
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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